William G Robbins

US Patent:

7098449, Aug 29, 2006

Filed:

Apr 30, 2004

Appl. No.:

10/836432

Inventors:

Raanan A. Miller - Newton MA, US
William L. Robbins - Newton MA, US

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

H01J 49/40

US Classification:

250287, 250290, 250281, 250282

Abstract:

Method and apparatus for high field asymmetric waveform ion mobility spectrometry in an electronic chip assembly,, including an input section, an ion filter and detection section and a control section, in which ion filtering proceeds in a planar chamber under influence of high field asymmetric periodic signals, with detection integrated into the flow path, for producing accurate, real-time, data for identification of a broad range of chemical compounds.

US Patent:

7619214, Nov 17, 2009

Filed:

Jul 6, 2006

Appl. No.:

11/482665

Inventors:

Raanan A. Miller - Chestnut Hill MA, US
William L. Robbins - Newton MA, US

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

B01D 59/44
H01J 49/00

US Classification:

250288, 250281, 250282, 250286, 250287, 250283, 250290, 250292, 386 46, 386125, 345418, 345440, 435 34, 702 19

Abstract:

Method and apparatus for high field asymmetric waveform ion mobility spectrometry in an electronic chip assembly, including an input section, an ion filter and detection section and a control section, in which ion filtering proceeds in a planar chamber under influence of high field asymmetric periodic signals, with detection integrated into the flow path, for producing accurate, real-time, data for identification of a broad range of chemical compounds.

US Patent:

20110247942, Oct 13, 2011

Filed:

Apr 12, 2010

Appl. No.:

12/758700

Inventors:

Jonathan J. Bernstein - Medfield MA, US
Mark J. Mescher - West Newton MA, US
William L. Robbins - Newton Center MA, US

International Classification:

C25C 1/02
C25C 7/02

US Classification:

205560, 204280, 204292, 204241, 205704

Abstract:

Electrodes are positioned substantially in contact with at least one surface of a solid to generate or absorb alkali metals when a voltage is applied between the electrodes.

US Patent:

56821670, Oct 28, 1997

Filed:

Jan 15, 1997

Appl. No.:

8/783071

Inventors:

Frank E. Mullen - No. Easton MA
William L. Robbins - Newton Center MA

Assignee:

The Charles Stark Draper Laboratory - Cambridge MA

International Classification:

H01Q 1138

US Classification:

343700MS

Abstract:

The present invention provides an antenna including a relatively thin substantially planar electrically conductive first layer substantially lying in a first plane, and a relatively thin substantially planar electrically conductive second layer substantially lying in a second plane. The first and second layers are disposed such that the first and second planes are substantially parallel and such that they are separated by a distance d. The second layer is smaller than and overlies the first layer and defines a first region extending between the second layer and a portion of the first layer underlying the second layer. The antenna further includes a first dielectric medium having a relatively high dielectric constant and disposed in the first region, and a second dielectric medium having a relatively low dielectric constant and disposed in a second region extending between the first layer and portions of the second plane overlying the first layer and excluding the first region.

US Patent:

40448169, Aug 30, 1977

Filed:

Jan 12, 1976

Appl. No.:

5/648315

Inventors:

Theodore H. Krueger - Lincoln MA
Robert Eller - Boston MA
John O'Brien - Winchester MA
William L. Robbins - Newton MA

International Classification:

B22D 2500
B22D 2716

US Classification:

164 63

Abstract:

The invention provides a new apparatus and method for forming thin metal parts of simple or intricate shape and depositing the same onto selected receiving surfaces. The parts may be in the form of wire leads which are bonded to the receiving surfaces. The invention consists in providing a hollow tool which includes a porous body with an exposed surface having a selected two-dimensional or three-dimensional geometry, immersing the surface of the porous body in a melt of a metal which will not wet the surface, pulling the tool away from the melt while applying a suction force to the porous body so that a portion of the melt will adhere to the surface, bringing the tool into contact with a receiving surface, and cooling the surface and removing the suction force so that the adhering portion of the melt will be deposited as a solid or partially solidified body onto the receiving surface. The deposited part will bond securely to the receiving surface if the latter is made of a material which is wetted by the melt.

US Patent:

48644650, Sep 5, 1989

Filed:

May 10, 1988

Appl. No.:

7/192098

Inventors:

William L. Robbins - Newton MA

Assignee:

The United States of America - Washington DC

International Classification:

H01G 410
H01G 700
H05K 116

US Classification:

361321

Abstract:

A two pole viad chip capacitor that is activatable from either of its sides having a plurality of ceramic layers in a stack, each and every layer having only two vias, a first via in a first region of each layer and a second via in a second region of each layer; a first conductor in each of the first vias; a second conductor in each of the second vias; a stack of first capacitor plates being on first alternate ceramic layers and each first plate being in electrical contact with a first conductor; and a stack of second capacitor plates, the second plates being on second alternate ceramic layers that are interdigitated with the first alternate ceramic layers and in electrical contact with a second conductor.

US Patent:

60206462, Feb 1, 2000

Filed:

Dec 5, 1997

Appl. No.:

8/985807

Inventors:

John J. Boyle - Natick MA
William L. Robbins - Newton Center MA

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

H01L 310203
H01L 2715
H01L 2348

US Classification:

257783

Abstract:

An integrated circuit (IC) die carrier assembly includes a thinned IC die mounted to a substrate or carrier. The IC die is mounted to the carrier via a thin layer of glass. The carrier facilitates fixturing and provides support during the lapping process used to thin the die. Ball bonding, wire bonding, thin film or thick film conductors can be used to interconnect the pads on the IC die to the pads on the carrier. The coefficients of the thermal expansion of the IC die and the carrier are closely matched to avoid damage to the IC die due to uneven expansion of the thinned IC die relative to the carrier. The IC die carrier assembly is better suited for ultrahigh vacuum and high temperature environments than conventional IC die carrier assemblies.

US Patent:

62815725, Aug 28, 2001

Filed:

Dec 5, 1997

Appl. No.:

8/986259

Inventors:

William L. Robbins - Newton Center MA

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

H01L 23053

US Classification:

257700

Abstract:

An integrated circuit (IC) header subassembly includes a spacer mounted to the header. The IC die assembly, consisting of an IC die or IC die carrier assembly, is mounted to spacer which is mounted to the header. The coefficient of thermal expansion of the spacer is selected to be between the coefficient of thermal expansion of the IC die assembly and the header minimize stresses due to thermal expansion and contraction. In addition, the spacer is substantially smaller in width and length and the IC die assembly and the header whereby the IC die assembly appears to be pedestal mounted. By minimizing the length of the contacting surfaces between the spacer and the IC die assembly, the risk of warping or cracking due to differences in thermal expansion can be reduced. This allows for much larger IC dies and pixel arrays to be used.