William Andrew Schwarz

US Patent:

7076699, Jul 11, 2006

Filed:

Sep 19, 2001

Appl. No.:

09/956302

Inventors:

Mukesh K. Puri - Fremont CA, US
Ghasi R. Agrawal - San Jose CA, US
William Schwarz - Austin TX, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 29/00

US Classification:

714710

Abstract:

A method for testing semiconductor devices advantageously increases manufacturing yields. The method includes generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pattern back out of the memory, comparing the at least one predetermined digital bit pattern read out from the memory against the at least one predetermined digital bit pattern written into the memory, and storing results of the comparison as the memory repair data. The writing and reading are performed a plurality of times, each time with a different voltage and clock frequency combination being applied to the wafer die. The memory repair data is programmed into the wafer die, and the wafer die is assembled into a packaged semiconductor device. The packaged semiconductor device is tested by causing the memory repair data programmed within the packaged semiconductor device to be transferred into the memory a plurality of times, each time with a different voltage and clock frequency combination being applied to the packaged semiconductor device.

US Patent:

58354298, Nov 10, 1998

Filed:

May 9, 1997

Appl. No.:

8/854076

Inventors:

William Schwarz - San Leandro CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700
G11C 1100

US Classification:

365201

Abstract:

A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During testing of the memory array, the weak test circuit controls the address decoder to decrease the voltage on the word lines so that it is less than the threshold voltage of the memory array transistors. The microprocessor then writes an inverted data to the memory array and then reads it. The read inverted data is sent to the display unit for comparison with a known template. By comparing the read inverted data to the template, defective memory cells can be identified.

US Patent:

59826819, Nov 9, 1999

Filed:

Oct 10, 1997

Appl. No.:

8/948920

Inventors:

William Schwarz - San Leandro CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

365201

Abstract:

A reconfigurable built-in self test circuit for enabling the debugging of an embedded device. In one embodiment, the write data path from the built-in self test module to the embedded device includes a multiplexer which is controlled by a debug signal. When the debug signal is de-asserted, the multiplexer forwards the write data from the built-in self test module to the embedded device, thereby allowing the self test to proceed in the hard wired manner. When the debug signal is asserted, the multiplexer forwards external data from the user to the embedded device, thereby allowing the user to execute customized tests on the embedded device. A second multiplexer is similarly placed in the expected data path from the built-in self test module to the comparator to allow the user to provide external data for comparison with output data from the embedded device when the debug signal is asserted. For all tests, the address and control data is provided by the built-in self test module to avoid the need to implement an external access to these data paths.

US Patent:

59094044, Jun 1, 1999

Filed:

Mar 27, 1998

Appl. No.:

9/049852

Inventors:

William Schwarz - San Leandro CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 700

US Classification:

365201

Abstract:

A method for testing a memory device which statistically characterizes the failure time for a subset of cells sampled from the memory array before performing testing of the memory array in general. The memory device includes a testing unit which determines the failure times for cells in the sample subset, and a parameter calculation unit which computes one or more statistical parameters from the failure times. These statistical parameters are then used to determine a refresh pause time which is used in a data retention test of the memory array. The testing method may be performed when power is applied to the memory device. Thus, the BIST method may provide for the accurate detection of memory faults in the memory array at any power-up temperature. In addition, the testing method may be performed after the memory array attains an operational temperature, or in response to an operating system command.