William M Shumate

US Patent:

49338986, Jun 12, 1990

Filed:

Jan 12, 1989

Appl. No.:

7/297472

Inventors:

Robert C. Gilberg - San Diego CA
Richard M. Knowles - San Diego CA
Paul Moroney - Cardiff-by-the-Sea CA
William A. Shumate - San Diego CA

Assignee:

General Instrument Corporation - New York NY

International Classification:

G11C 700
G06F 1300

US Classification:

365 53

Abstract:

An integrated circuit chip containing a secure area in which secure data is processed and/or stored, includes a semiconductive layer containing diffusions defining circuit element components; a first conductive layer coupled to the semiconductive layer to interconnect the components to thereby define circuit elements for distributing, storing processing and/or affecting the processing of secure data; and a second conductive layer overlying the circuit elements to thereby define a secure area in which the circuit elements are shielded from inspection, and coupled to the circuit elements for conducting to the circuit elements a predetermined signal that is essential to an intended function of the shielded circuit elements, whereby removal of the second conductive layer will prevent the predetermined essential signal from being provided to the circuit elements and thereby prevent the intended function.

US Patent:

48797200, Nov 7, 1989

Filed:

Mar 10, 1988

Appl. No.:

7/166187

Inventors:

William A. Shumate - San Diego CA
Daniel R. Kindred - San Diego CA
Franklin P. Antonio - Del Mar CA
Steven H. Gardner - San Diego CA
Krishnanand Kelkar - La Jolla CA
Thomas R. Bilotta - Vista CA
Steven L. Rogers - San Diego CA

Assignee:

M/A-Com Government Systems, Inc. - San Diego CA

International Classification:

G06F 1110

US Classification:

371 43

Abstract:

A decoding system capable of outputting Viterbi-decoding-algorithm-decoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm to produce the decoded data. The system includes a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus. Each of the decoders in the ring includes an input buffer, timing controller, decoding processor and output buffer. The input buffer responds to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data. The timing contoller provides a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder. The decoding processor processes the buffered block of coded data at a given rate to produce decoded data.

US Patent:

50143107, May 7, 1991

Filed:

Dec 18, 1989

Appl. No.:

7/455554

Inventors:

Gordon K. Walker - Escondido CA
William A. Shumate - San Diego CA
Krishnanand Kelkar - San Diego CA

Assignee:

General Instrument Corporation - New York NY

International Classification:

H04N 716

US Classification:

380 10

Abstract:

A video scrambling system scrambles adjacent sequentially odd and even video information lines of a video frame by simultaneously storing in a memory a pair of such adjacent lines; and forming a pair of scrambled video information lines by retrieving from the memory a segment of one of the stored video information lines followed by a segment of the other stored video information line, and by shifting the phase of one of the retrieved segments of the scrambled video information line in relation to the other retrieved segment of said scrambled video information line by an odd multiple of one-half the phase of the chrominance information cycle. This phase shift causes the phase relationship of all segments with respect to the color reference signal to be the same; and as a result there is no differential hue shift in the descrambled signal. In a complementary descrambling system, the two retrieved segments of each descrambled video information line are retrieved consecutively without an intervening phase shift. Security of the scrambled signal against unauthorized descrambling is enhanced by delaying the provision of an encryption keystream to a control unit that sets the cutpoint between the segments in accordance with said keystream, and further using the keystream to set the amount of said delay.

US Patent:

50832930, Jan 21, 1992

Filed:

Jan 12, 1989

Appl. No.:

7/297137

Inventors:

Robert C. Gilberg - San Diego CA
Paul Moroney - Cardiff-By-The-Sea CA
William A. Shumate - San Diego CA

Assignee:

General Instrument Corporation - New York NY

International Classification:

G11C 700
G11C 1602
G11C 1300

US Classification:

36518901

Abstract:

An integrated circuit chip in which alteration of secure data stored in a predetermined location of a memory on the chip may be prevented. In one embodiment, the chip includes a memory having a plurality of memory locations, with a predetermined location being for the storage of unalterable secure data; a memory control logic circuit coupled to the memory by an address bus for causing data to be stored in locations of the memory indicated by address signals provided on the address bus; a fuse element having an initial state and an irreversibly altered state; means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal; and a decoder coupled to the fuse element, the memory control circuit and the address bus for monitoring the state of the fuse element and said address signals, and for preventing the memory control circuit from causing data to be stored in the predetermined memory location after the state of the fuse element has been altered irreversibly whenever the predetermined memory location is indicated by an address signal on the address bus. In another embodiment, the chip, includes a first memory having a plurality of memory locations, with a predetermined location being for the storage of unalterable secure data; a second memory; means for enabling a data pattern to be stored in the second memory; a memory control logic circuit coupled to the first and second memories for causing data to be stored in the predetermined location of the first memory in response to a write signal whenever the second memory contains a predetermined data pattern; means coupled to the second memory for enabling the contents of the second memory to be erased; a fuse element having an initial state and an irreversibly altered state; and means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal; wherein the fuse element is coupled to the means for enabling a data pattern to be stored in the second memory so as to enable said data pattern storage only prior to the state of the fuse element being irreversibly altered.