William T Stone

US Patent:

20070268057, Nov 22, 2007

Filed:

Mar 20, 2006

Appl. No.:

11/386121

Inventors:

Vandana Gopal - San Diego CA, US
Mohanraj Umapathy - San Marcos CA, US
Philippe Bergman - San Diego CA, US
William Stone - San Diego CA, US

International Classification:

G06F 7/00
G06F 1/04

US Classification:

327295000

Abstract:

Methods and apparatus for applying changes to a group of objects. A method is provided for applying one or more changes to a group of objects. The method includes communicating the one or more changes to the group of objects at one or more communication times, and receiving one or more acknowledgement signals. The method also includes determining a sync time indicator associated with a selected object, wherein the sync time indicator indicates a time when a selected acknowledgement signal has been received from the selected object for each change communicated prior to the sync time indicator, and comparing the sync time indicator with a last communication time to determine whether the one or more changes have been applied to the selected object.

US Patent:

20220392867, Dec 8, 2022

Filed:

Jun 4, 2021

Appl. No.:

17/339830

Inventors:

- San Diego CA, US
Charles David PAYNTER - Encinitas CA, US
Ryan LANE - San Diego CA, US
Jianwen XU - San Diego CA, US
William STONE - San Diego CA, US

International Classification:

H01L 23/00
H01L 23/498
H01L 23/538
H01L 25/10
H01L 21/48
H01L 21/56
H01L 23/31

Abstract:

A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

US Patent:

20220344250, Oct 27, 2022

Filed:

Apr 22, 2021

Appl. No.:

17/237828

Inventors:

- San Diego CA, US
Giridhar Nallapati - San Diego CA, US
William Stone - San Diego CA, US
Jianwen Xu - San Diego CA, US
Jonghae Kim - San Diego CA, US
Periannan Chidambaram - San Diego CA, US
Ahmer Syed - San Diego CA, US

International Classification:

H01L 23/498
H01L 49/02
H01L 21/48

Abstract:

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

US Patent:

20190287929, Sep 19, 2019

Filed:

May 31, 2019

Appl. No.:

16/428441

Inventors:

- San Diego CA, US
William Michael STONE - San Diego CA, US

International Classification:

H01L 23/00
H01L 23/31
H01L 23/498
H01L 21/56
H01L 23/528
H01L 21/768
H01L 23/522

Abstract:

An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

US Patent:

20180151513, May 31, 2018

Filed:

Nov 1, 2017

Appl. No.:

15/800837

Inventors:

- San Diego CA, US
William Michael STONE - San Diego CA, US

International Classification:

H01L 23/00
H01L 23/31
H01L 21/56
H01L 23/522
H01L 23/528
H01L 21/768

Abstract:

An integrated circuit (IC) device includes a device layer and a passivation layer, where the passivation layer has vias formed in an interior region of the passivation layer that are larger than vias formed in a perimeter region of the passivation layer. As such, a varying diameter via layer is provided. The interior region vias may be configured to reduce a risk of damage to the IC device due to tensile stress, with sizes or shapes selected based on the amount of tensile stress expected to occur during subsequent use of the IC device. The perimeter region vias may be configured to reduce a risk of damage to the IC device due to sheer stress, with sizes or shapes selected based on the amount of sheer stress expected to occur during subsequent assembly or use of the IC device. Method and apparatus examples are described for use with flip-chip dies.

US Patent:

20170294422, Oct 12, 2017

Filed:

Aug 2, 2016

Appl. No.:

15/225910

Inventors:

- San Diego CA, US
William Stone - San Diego CA, US
John Holmes - San Diego CA, US
Christopher Healy - San Diego CA, US
Rajendra Pendse - San Diego CA, US
Sun Yun - San Diego CA, US

International Classification:

H01L 25/10
H01L 25/00

Abstract:

A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

US Patent:

20170271175, Sep 21, 2017

Filed:

Mar 15, 2017

Appl. No.:

15/460062

Inventors:

- San Diego CA, US
John Patrick HOLMES - San Diego CA, US
Michael James SOLIMANDO - San Diego CA, US
Sun YUN - San Diego CA, US
William Michael STONE - San Diego CA, US
Rajendra PENDSE - Fremont CA, US

International Classification:

H01L 21/56
H01L 23/00
H01L 23/498

Abstract:

Disclosed is a die packaging structure comprising a semiconductor die, an encapsulant layer disposed around the semiconductor die, wherein a backside surface of the semiconductor die is exposed, and a conductive layer coupled to the semiconductor die, the conductive layer comprising a plurality of conductive pillar bumps, wherein a bump density of the plurality of conductive pillar bumps is greater than 5%, wherein the encapsulant layer is further disposed between the plurality of conductive bumps, and wherein the encapsulant layer is disposed between the plurality of conductive bumps using a mold underfill (MUF) process. A method of forming the same is also disclosed.

US Patent:

20150318229, Nov 5, 2015

Filed:

May 1, 2015

Appl. No.:

14/702276

Inventors:

- San Diego CA, US
Lizabeth Ann KESER - San Diego CA, US
William STONE - San Diego CA, US
Steve Joseph BEZUK - San Diego CA, US
Nicholas Ka Ming YU - San Diego CA, US

International Classification:

H01L 23/31
H01L 23/532
H01L 23/498
H01L 23/528

Abstract:

A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer.