William D Whiteman

US Patent:

5881293, Mar 9, 1999

Filed:

Aug 20, 1996

Appl. No.:

8/699921

Inventors:

Sompong Paul Olarig - Cypress TX
Dale J. Mayer - Houston TX
William F. Whiteman - Cypress TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1300

US Classification:

395733

Abstract:

A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

US Patent:

6434626, Aug 13, 2002

Filed:

Jan 14, 1999

Appl. No.:

09/229885

Inventors:

Ramkrishna V. Prakash - Houston TX
William F. Whiteman - Cypress TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

709238, 709220, 709224, 709313

Abstract:

A method and apparatus for reducing latency caused by cumulative point-to-point messaging associated with network performance monitoring in SAN-attached I O architectures. In a computer system, a performance monitoring OSM associated with a first node generates status request messages to a first multicast ISM residing on a first governor IOP associated with a first node for requesting the status from all nodes. The first multicast ISM generates status request messages to all node devices and node IOPs and to a second multicast ISM residing on a node governor IOP. The second multicast ISM generates status request messages to all node devices and node IOPs. One or more âunhealthyâ device response messages may be sent to the performance monitoring OSM containing the TID of the âunhealthyâ device to allow a subsequent point-to-point detailed status request message to be issued. For âhealthyâ nodes, a response message is issued to an adjacent governor IOP with an âall fineâ indication and the TID set to the TID of the governor IOP. If all nodes in the network are âhealthyâ, an âall fineâ indication is passed to the performance monitoring OSM with the TID set to the TID of the governor IOP of the performance monitoring node.

US Patent:

6742072, May 25, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/652321

Inventors:

Ramkrishna V. Prakash - Houston TX
Sompong P. Olarig - Cypress TX
William F. Whiteman - Cypress TX

Assignee:

Hewlett-Packard Development Company, LP. - Houston TX

International Classification:

G06F 1341

US Classification:

710305, 709213, 709248

Abstract:

A new technique for transferring data between nodes of a clustered computing system is disclosed. In one aspect, the invention includes a cluster node comprising a system bus; a memory device; and an internodal interconnect. The internodal interconnect is electrically connected to the system bus and includes a remote connection port. The internodal interconnect is capable of transferring data from the memory device and through the remote connection port. In a second aspect, a the invention includes method for internodal data transfer in a clustered computing system. Each of at least two clusters includes an internodal interconnect electrically connected to a system bus and a memory device to the system bus. The method itself comprises requesting a data transfer and then transferring the requested data. The requested data is transferred from the memory device in a first cluster node to the memory device in a second cluster node via the internodal interconnects in the first and second cluster nodes.

US Patent:

20030126283, Jul 3, 2003

Filed:

Dec 31, 2001

Appl. No.:

10/039125

Inventors:

Ramkrishna Prakash - Houston TX, US
David Abmayr - Spring TX, US
Jeffrey Hilland - Cypress TX, US
James Fouts - Bellevue WA, US
Scott Johnson - Round Rock TX, US
William Whiteman - Cypress TX, US

International Classification:

G06F015/173

US Classification:

709/238000

Abstract:

A system provides a router node to bridge a LAN and a System Area Network (SAN). The router node distributes LAN traffic across the SAN using a router management agent (RMA) and a filter agent (FA); the RMA includes a session management agent (SMA), a policy management agent (PMA) and a routing agent (RA); the SMA manages connections between remote clients and SAN nodes; the PMA maintains system operation policies; the RA with the FA direct LAN packets to SAN nodes; the FA handles conversion between a SAN protocol and a LAN protocol for packets within the SAN/LAN architecture. The cluster nodes include a node management agent (NMA); the NMA includes an SMA and PMA; these two agents perform the same functions as those in the router node; and a management node sets policies on the router node and includes a monitoring agent to query router node statistics.

US Patent:

60413778, Mar 21, 2000

Filed:

Feb 2, 1999

Appl. No.:

9/243235

Inventors:

Dale J. Mayer - Houston TX
Sompong Paul Olarig - Cypress TX
William F. Whiteman - Cypress TX
David F. Heinrich - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1300

US Classification:

710113

Abstract:

A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

US Patent:

62498304, Jun 19, 2001

Filed:

Mar 21, 2000

Appl. No.:

9/532109

Inventors:

Dale J. Mayer - Houston TX
Sompong Paul Olarig - Cypress TX
William F. Whiteman - Cypress TX
David F. Heinrich - Tomball TX

Assignee:

Compaq Computer Corp. - Houston TX

International Classification:

G06F 1300

US Classification:

710113

Abstract:

A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

US Patent:

59110554, Jun 8, 1999

Filed:

Jun 5, 1996

Appl. No.:

8/658634

Inventors:

William F. Whiteman - Cypress TX
Alan L. Goodrum - Tomball TX
B. Tod Cox - Houston TX
Barry S. Basile - Houston TX
Brian T. Purcell - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1300

US Classification:

395309

Abstract:

A computer system has a central processing unit and a bus. A first bus device and a second bus device are connected to the bus. A circuit is connected to configure the second bus device to be addressable by the central processing unit via the bus only by interaction with the first bus device. The first bus device may be an I. sub. 2 O processor, and the second bus device may be an I. sub. 2 O subordinate bus device.

US Patent:

60527498, Apr 18, 2000

Filed:

Nov 14, 1997

Appl. No.:

8/970367

Inventors:

Brian T. Purcell - Tomball TX
Pamela M. Cook - Spring TX
William F. Whiteman - Cypress TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1310
G06F 1320
G06F 902
G06F 944

US Classification:

710 71

Abstract:

Apparatus, and an associated method, converts a conventional computer peripheral device, such as an I/O (input/output) subsystem into an I. sub. 2 O-aware device. An IOP mounted upon a connector card is connected to a computer bus to which the conventional computer peripheral device is connected. Once connected, the IOP, together with the conventional computer peripheral device form an I. sub. 2 O-aware device.