Wing C Chan

US Patent:

6633935, Oct 14, 2003

Filed:

Sep 27, 2000

Appl. No.:

09/671939

Inventors:

Wing Chan - Pleasanton CA
David L. Griffith - Pleasanton CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

710100

Abstract:

An on line serviceable computing system employing a small computer system interface (SCSI) bus architecture connecting two host computers to at least one additional shared device including a termination adapter circuit that can sense when a SCSI termination at the end of the SCSI bus is lost and automatically switch in a new SCSI bus termination to thereby ensure that the bus is terminated at both ends as required for continuous operation.

US Patent:

7110732, Sep 19, 2006

Filed:

Mar 19, 2002

Appl. No.:

10/102428

Inventors:

Mohamed A. I. Mostafa - Santa Clara CA, US
Sherif Embabi - Plano TX, US
Moderage C. Fernando - Plano TX, US
Wing Kan Chan - Allen TX, US
Charles Gore, Jr. - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 1/26
H04B 15/00

US Classification:

455130, 455313, 455334, 37524021, 375322, 375350

Abstract:

A subsampling receiver () for converting an RF signal to baseband is disclosed. The subsampling receiver () may be implemented into a wireless communications device (), such as a wireless telephone handset. In one disclosed embodiment, the receiver () includes a sample and hold circuit () that samples a bandpass filtered input modulated signal at the subsampling frequency (f) that is well below the RF carrier frequency but twice the bandwidth (BW) of the payload; the sampled signal is digitized, and applied to two digital mixers (I, Q) to produce in-phase and quadrature components (I,Q) of the payload. In another embodiment, the receiver () includes two sample and hold circuits (I, Q) to sample the filtered signal at different phases of the sampling frequency, to produce the in-phase and quadrature digital components. In a third embodiment, the receiver () includes an analog mixer () to downconvert the RF input to an intermediate frequency, prior to digitization and digital mixing at quadrature phase.

US Patent:

20060235901, Oct 19, 2006

Filed:

Apr 18, 2005

Appl. No.:

11/109167

Inventors:

Wing Chan - Cupertino CA, US

International Classification:

G06F 17/30

US Classification:

707201000

Abstract:

A method for performing dynamic burst transfers between a first computer system and a second computer system includes monitoring time delay associated with communicating messages between the first computer system and the second computer system. Contention for resources in at least one of the first computer system and the second computer system can also be monitored. A transfer mode indicating whether data should be transferred in one message or multiple messages between the first and second computer systems is determined based on the time delay and/or the level of contention for resources.

US Patent:

48211702, Apr 11, 1989

Filed:

Apr 17, 1987

Appl. No.:

7/040513

Inventors:

David L. Bernick - Felton CA
Kenneth K. Chan - San Jose CA
Wing M. Chan - Fremont CA
Yie-Fong Dan - San Jose CA
Duc M. Hoang - San Jose CA
Zubair Hussain - San Jose CA
Geoffrey I. Iswandhi - Sunnyvale CA
James E. Korpi - Santa Clara CA
Martin W. Sanner - Los Gatos CA
Jay A. Zwagerman - Saratoga CA
Steven G. Silverman - Santa Clara CA
James E. Smith - Sunnyvale CA

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1516

US Classification:

364200

Abstract:

In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer.

US Patent:

61924334, Feb 20, 2001

Filed:

Jul 14, 1998

Appl. No.:

9/115144

Inventors:

Wing Chan - Pleasanton CA
David L. Griffith - Pleasanton CA

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1300

US Classification:

710101

Abstract:

An on line serviceable computing system employing a small computer system interface (SCSI) bus architecture connecting two host computers to at least one additional shared device including a termination adapter circuit that can sense when a SCSI termination at the end of the SCSI bus is lost and automatically switch in a new SCSI bus termination to thereby ensure that the bus is terminated at both ends as required for continuous operation.

US Patent:

52376583, Aug 17, 1993

Filed:

Oct 1, 1991

Appl. No.:

7/769538

Inventors:

Mark Walker - Los Gatos CA
Albert S. Lui - San Jose CA
Harald W. Sammer - Friedrichsdorf, DE
Wing M. Chan - Pleasanton CA
William T. Fuller - San Jose CA

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1300

US Classification:

395200

Abstract:

A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

US Patent:

57713448, Jun 23, 1998

Filed:

Sep 9, 1996

Appl. No.:

8/709787

Inventors:

Wing Ming Chan - Pleasanton CA
Wouter Senf - Blaricum, NL
Timothy C. K. Chou - Palo Alto CA
Mark H. Roettgering - Sunnyvale CA
Nusret Yurutucu - Gilroy CA
Craig F. Adams - San Jose CA

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1300

US Classification:

39518205

Abstract:

First and second data processing systems located at first and second sites are configured with the first data processing system having a primary memory unit at the first site and a mirror memory unit at the second site with the first and second sites coupled by a single-mode optical fiber. Fiber optic switches at the first and second sites can be reconfigured to coupled the mirror disc to the second data processing system with minimal delay.

US Patent:

49981986, Mar 5, 1991

Filed:

Apr 7, 1988

Appl. No.:

7/178667

Inventors:

Wing M. Chan - Fremont CA

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

In a data processing system, a device controller, configured to control data transfers between a processor unit and a peripheral device on an input/output bus, is provided with apparatus that permits a data transfer cycle to continue until all data has been transferred, or to allow for interruption of the data transfer cycle by another device controller requesting access to the input/output via a request signal. During a data transfer cycle the apparatus resonds to detection of the request signal to interrupt the data transfer cycle after a predetermined number of data words are transferred, permitting access to the input/output bus for other of the device controllers. In absence of the request signal, the apparatus permits the data transfer to continue until all data has been transferred between the peripheral device and the processor unit.