Wolfram Christina Sauer

US Patent:

7283072, Oct 16, 2007

Filed:

Mar 30, 2006

Appl. No.:

11/278118

Inventors:

Piotr M. Plachta - Toronto, CA
Wolfram Sauer - Austin TX, US
Balakrishna Raghavendra Iyer - San Jose CA, US
Steven Wayne White - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 7/00

US Classification:

341107, 341 87

Abstract:

Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favours longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.

US Patent:

7454597, Nov 18, 2008

Filed:

Jan 2, 2007

Appl. No.:

11/618948

Inventors:

Krishnan K. Kailas - Tarrytown NY, US
Ravi Nair - Briarcliff Manor NY, US
Sumedh W. Sathaye - Cary NC, US
Wolfram Sauer - Austin TX, US
John-David Wellman - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712206, 712213, 712215, 712240

Abstract:

A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a rename map of registers for each register in the schedule, and a list of register names used in the schedule. The schedule exploits instruction-level parallelism in executing out-of-order instructions. The processor core includes a schedule cache that is configured to store schedules, a shared cache configured to store both I-side and D-side cache data, and an execution resource for requesting a schedule to be executed from the schedule cache. The processor core further includes a scheduler disposed between the schedule cache and the cache. The scheduler creating the schedule using branch execution history from a branch history table to create the instructions when the schedule requested by the execution resource is not found in the schedule cache.

US Patent:

7460033, Dec 2, 2008

Filed:

Dec 28, 2006

Appl. No.:

11/617610

Inventors:

Balakrishna Raghavendra Iyer - San Jose CA, US
Piotr M. Plachta - Toronto, CA
Wolfram Sauer - Austin TX, US
Steven W. White - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 7/34

US Classification:

341 51, 341 50, 341107

Abstract:

Some aspects of the invention provide methods for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

US Patent:

7627742, Dec 1, 2009

Filed:

Apr 10, 2007

Appl. No.:

11/733589

Inventors:

Pradip Bose - Yorktown Heights NY, US
Alper Buyuktosunoglu - White Plains NY, US
Michael Karl Gschwind - Chappaqua NY, US
Ravi Nair - Briarcliff Manor NY, US
Robert Alan Philhower - Valley Cottage NY, US
Wolfram Sauer - Austin TX, US
Raymond Cheung Yeung - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/32

US Classification:

712220, 712205

Abstract:

An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.

US Patent:

7779234, Aug 17, 2010

Filed:

Oct 23, 2007

Appl. No.:

11/877391

Inventors:

James W. Bishop - Endwell NY, US
Hung Q. Le - Austin TX, US
Dung Q. Nguyen - Austin TX, US
Wolfram Sauer - Austin TX, US
Benjamin W. Stolt - Austin TX, US
Michael T. Vaden - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712207

Abstract:

The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.

US Patent:

7809933, Oct 5, 2010

Filed:

Jun 7, 2007

Appl. No.:

11/759350

Inventors:

David S. Levitan - Austin TX, US
Wolfram Sauer - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712239

Abstract:

A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address. Since there are no other target instructions that were fetched, no flush is needed if that target address is the correct address, i. e.

US Patent:

7973680, Jul 5, 2011

Filed:

Jul 14, 2008

Appl. No.:

12/172557

Inventors:

Balakrishna Raghavendra Iyer - San Jose CA, US
Piotr M. Plachta - Toronto, CA
Wolfram Sauer - Austin TX, US
Steven W. White - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 7/34

US Classification:

341 51, 341 50, 341107

Abstract:

A system and computer readable storage medium for creating an in-memory physical dictionary for data compression are provided. A new heuristic is defined for converting each of a plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes. Each of the physical nodes are placed into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

US Patent:

8037034, Oct 11, 2011

Filed:

Jul 23, 2007

Appl. No.:

11/781833

Inventors:

Piotr M. Plachta - Toronto, CA
Wolfram Sauer - Austin TX, US
Balakrishna Raghavendra Iyer - San Jose CA, US
Steven Wayne White - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/00
G06F 17/00

US Classification:

707693

Abstract:

Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favors longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.