Won Bok Choi

US Patent:

20230025601, Jan 26, 2023

Filed:

Jul 14, 2022

Appl. No.:

17/812646

Inventors:

- Boise ID, US
Scott Schlachter - San Jose CA, US
Won Ho Choi - Santa Clara CA, US

International Classification:

G06F 3/06

Abstract:

Methods, systems, and devices for initializing memory systems are described. A memory system may transmit, to a host system over a first channel, signaling indicative of a first set of values for a set of parameters associated with communicating information over a second channel between a storage device of the memory system and a memory device of the memory system. The host system may transmit, to the memory system, additional signaling associated with the first set of values for the set of parameters. For instance, the host system may transmit a second set of values for the set of parameters, an acknowledgement to use the first set of values, or a command to perform a training operation on the second channel to identify a second set of values for the set of parameters. The memory system may communicate the information over the second channel based on the additional signaling.

US Patent:

20210406672, Dec 30, 2021

Filed:

Jun 26, 2020

Appl. No.:

16/912846

Inventors:

- Addison TX, US
Won Ho Choi - Santa Clara CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

G06N 3/08
G06N 3/063
G06N 3/04

Abstract:

Non-volatile memory structures for performing compute in memory inferencing for neural networks are presented. To improve performance, both in terms of speed and energy consumption, weight matrices are replaced with their singular value decomposition (SVD) and use of a low rank approximations (LRAs). The decomposition matrices can be stored in a single array, with the resultant LRA matrices requiring fewer weight values to be stored. The reduced sizes of the LRA matrices allow for inferencing to be performed more quickly and with less power. In a high performance and energy efficiency mode, a reduced rank for the SVD matrices stored on a memory die is determined and used to increase performance and reduce power needed for an inferencing operation.

US Patent:

20210397930, Dec 23, 2021

Filed:

Jun 22, 2020

Appl. No.:

16/908576

Inventors:

- San Jose CA, US
Won Ho Choi - Santa Clara CA, US

Assignee:

Western Digital Technologies, Inc. - San Jose CA

International Classification:

G06N 3/063
G11C 11/409
G06F 7/544
G06F 7/523
G06F 7/50
G06K 9/62

Abstract:

A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.

US Patent:

20210397974, Dec 23, 2021

Filed:

Jul 28, 2020

Appl. No.:

16/941178

Inventors:

- Addison TX, US
Won Ho Choi - Santa Clara CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

G06N 3/10
G06F 7/544
G06F 12/02

Abstract:

Anon-volatile memory structure capable of storing weights for layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. An in-array multiplication can be performed between multi-bit valued inputs, or activations, for a layer of the DNN and multi-bit valued weights of the layer. Each bit of a weight value is stored in a binary valued memory cell of the memory array and each bit of the input is applied as a binary input to a word line of the array for the multiplication of the input with the weight. To perform a multiply and accumulate operation, the results of the multiplications are accumulated by adders connected to sense amplifiers along the bit lines of the array. The adders can be configured to multiple levels of precision, so that the same structure can accommodate weights and activations of 8-bit, 4-bit, and 2-bit precision.

US Patent:

20210334338, Oct 28, 2021

Filed:

Jul 8, 2021

Appl. No.:

17/370716

Inventors:

- San Jose CA, US
Pi-Feng Chiu - Milpitas CA, US
Minghai Qin - Milpitas CA, US
Won Ho Choi - San Jose CA, US

International Classification:

G06F 17/16
G11C 13/00
G06N 3/08

Abstract:

An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

US Patent:

20210325957, Oct 21, 2021

Filed:

Apr 21, 2020

Appl. No.:

16/854677

Inventors:

- San Jose CA, US
Cyril GUYOT - San Jose CA, US
Won Ho CHOI - San Jose CA, US

International Classification:

G06F 1/3296
G06N 3/04
G06N 3/08

Abstract:

Certain aspects of the present disclosure provide a method for performing multimode inferencing, comprising: receiving machine learning model input data from a requestor; processing the machine learning model input data with a machine learning model using processing hardware at a first power level to generate first output data; selecting a second power level for the processing hardware based on comparing the first output data to a threshold value; processing the machine learning model input data with the machine learning model using the processing hardware at the second power level to generate second output data; and sending second output data to the requestor.

US Patent:

20210326110, Oct 21, 2021

Filed:

Apr 16, 2020

Appl. No.:

16/850395

Inventors:

- Addison TX, US
Pi-Feng Chiu - Milpitas CA, US
Won Ho Choi - Santa Clara CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

G06F 7/523
G11C 13/00

Abstract:

Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

US Patent:

20210264958, Aug 26, 2021

Filed:

May 13, 2021

Appl. No.:

17/319991

Inventors:

- San Jose CA, US
Yoocharn Jeon - Palo Alto CA, US
Won Ho Choi - Santa Clara CA, US
Cyril Guyot, JR. - San Jose CA, US
Yuval Cassuto - Haifa, IL

Assignee:

WESTERN DIGITAL TECHNOLOGIES, INC. - San Jose CA

International Classification:

G11C 11/16
G06F 12/02

Abstract:

An apparatus is provided that includes a memory device including a plurality of sub-arrays, and a memory controller. The memory controller is configured to determine a value of a parameter of a corresponding write pulse for each bit of a word based on a relative importance of each bit, and write each bit of the word to a corresponding one of the plurality of sub-arrays using the corresponding write pulses.