Xi I Li

US Patent:

7476578, Jan 13, 2009

Filed:

Jul 12, 2007

Appl. No.:

11/776710

Inventors:

Kangguo Cheng - Beacon NY, US
Xi Li - Somers NY, US
Richard S. Wise - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438154, 257369

Abstract:

A process for finFET spacer formation generally includes depositing, in order, a conformal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.

US Patent:

7494891, Feb 24, 2009

Filed:

Sep 21, 2006

Appl. No.:

11/533928

Inventors:

Kangguo Cheng - Beacon NY, US
Johnathan E. Faltermeier - Delanson NY, US
Xi Li - Somers NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438386, 438243, 257301, 257E21651

Abstract:

A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.

US Patent:

7498271, Mar 3, 2009

Filed:

Jun 24, 2008

Appl. No.:

12/145035

Inventors:

Ricardo A. Donaton - Cortlandt Manor NY, US
Rashmi Jha - Wappingers Falls NY, US
Siddarth A. Krishnan - Peekskill NY, US
Xi Li - Somers NY, US
Renee T. Mo - Briarcliff Manor NY, US
Naim Moumen - Walden NY, US
Wesley C. Natzle - New Paltz NY, US
Ravikumar Ramachandran - Pleasantville NY, US
Richard S. Wise - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/31

US Classification:

438775, 438777, 438788, 438709, 438710

Abstract:

The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

US Patent:

7560360, Jul 14, 2009

Filed:

Aug 30, 2006

Appl. No.:

11/468472

Inventors:

Kangguo Cheng - Beacon NY, US
David M. Dobuzinsky - New Windsor NY, US
Xi Li - Somers NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438432, 438714, 438723, 438733, 438738, 438740, 257E21013, 257E21014, 257E21235, 257E21258, 257E21578

Abstract:

Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

US Patent:

7560387, Jul 14, 2009

Filed:

Jan 25, 2006

Appl. No.:

11/275707

Inventors:

Scott D. Allen - Dumont NJ, US
Kangguo Cheng - Beacon NY, US
Xi Li - Somers NY, US
Kevin R. Winstel - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/311

US Classification:

438702, 438719, 438723, 438724, 257E21002

Abstract:

Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

US Patent:

7682922, Mar 23, 2010

Filed:

Jan 18, 2007

Appl. No.:

11/624385

Inventors:

Anil K. Chinthakindi - Hay Market VA, US
Xi Li - Somers NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438386, 438389, 438391, 438392

Abstract:

A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.

US Patent:

7683416, Mar 23, 2010

Filed:

Nov 6, 2007

Appl. No.:

11/935698

Inventors:

Anil K. Chinthakindi - Haymarket VA, US
Xi Li - Somers NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/108

US Classification:

257301, 257302, 257304, 257305, 257E27092, 257E27095, 257E29346, 257E21396

Abstract:

A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.

US Patent:

7709320, May 4, 2010

Filed:

Jun 28, 2006

Appl. No.:

11/427065

Inventors:

Kangguo Cheng - Beacon NY, US
Xi Li - Somers NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8242
H01L 27/108

US Classification:

438243, 438386, 257 71, 257E27084, 257E21646

Abstract:

A method of forming a trench capacitor and memory cells using the trench capacitor. The method includes: forming an opening in a masking layer; and forming a trench in the substrate through the opening, the trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into the substrate, the upper region of the trench adjacent to the top surface of the substrate having a vertical sidewall profile and a first width in the horizontal direction, the middle region of the trench having a tapered sidewall profile, a width in a horizontal direction of the middle region at a juncture of the upper region and the middle region being the first width and being greater than a second width in the horizontal direction of the middle region at a juncture of the middle region and the lower region.