Xia Li

US Patent:

6409878, Jun 25, 2002

Filed:

Oct 5, 2000

Appl. No.:

09/680558

Inventors:

Xia Li - Fremont CA
Joseph Vu - San Jose CA
Mohammad Massoodi - Los Altos CA
Jose Hulog - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

C23F 102

US Classification:

15634523

Abstract:

An automatic decapsulation system for a device is disclosed. The system comprises an etch plate, an etch head, an acid resistant, high heat endurance and flexible sheet coupled to the etch plate, and a rubber gasket disposed between the sheet and the etch head. The sheet provides a precise etch window and a self-aligning gasket for the device. The rubber gasket creates a tight seal between the device, the sheet, and the etch head. A system in accordance with the present invention utilizes an acid resistant, high heat endurance and flexible sheet in combination with a rubber gasket to seal the device for decapsulation and to provide a well-defined etch window. In addition, the sheet being utilized as the gasket is also utilized as the fixture, thereby eliminating the need to align the gasket to the metal fixture utilized in the conventional system.

US Patent:

6517666, Feb 11, 2003

Filed:

Mar 27, 2001

Appl. No.:

09/818382

Inventors:

Xia Li - Fremont CA
Jose Hulog - San Jose CA
Mohammad Massoodi - Los Altos CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

15634511

Abstract:

An automatic decapsulation system for a device is disclosed. The system comprises an etch plate, an etch head, a sheet coupled to the etch head, a rubber gasket disposed between the etch head and the sheet, and an integrated spacer and protection plate for securing the device without damaging the backside of the device during decapsulation. In one embodiment of the present invention, the integrated spacer and protection plate is adjustable to accommodate devices of varying sizes.

US Patent:

6521486, Feb 18, 2003

Filed:

Aug 24, 2000

Appl. No.:

09/645923

Inventors:

Xia Li - Fremont CA
Reid Hirata - Santa Clara CA
Michael Coiner - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

438118, 438 18, 438126

Abstract:

A method, and system for reducing switching noise on a device, and an improved capacitor-integrated device is disclosed. At least one conductive line is deposited within a device. Additionally, at least one capacitor is attached to the at least one conductive line. Once the capacitor is attached to the conductive line, an improved capacitor-integrated circuit device results. The method and system of the present invention provides for the addition of at least one capacitor to be added between the power supply pins on at least one IC device. By doing so, switching signal noise is reduced. As a result of the method and system of the present invention, the resulting improved device can be efficiently used to check various qualities such as the level of ground bouncing noise, or switching signal noise reduction, without changing the circuit design of the device.

US Patent:

6677169, Jan 13, 2004

Filed:

Aug 2, 2001

Appl. No.:

09/922417

Inventors:

Xia Li - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2166

US Classification:

438 15, 438 14, 438 16

Abstract:

A method and system for preparing a device for analysis is disclosed. In the present invention, the device to be prepared includes a semiconductor die coupled to a first surface of a package substrate. The first surface of the package substrate includes an interconnect pattern for electrically coupling the semiconductor die to a plurality of solder ball connectors disposed on a second surface of the package substrate. The method and system for preparing the device for backside analysis comprises removing the plurality of solder ball connectors, exposing the interconnect pattern, and then exposing a backside of the semiconductor die. The method further includes preparing the backside of the semiconductor die for diagnostic testing. Electrical contact with the semiconductor die is established via the exposed interconnect pattern.

US Patent:

7029595, Apr 18, 2006

Filed:

Aug 21, 2002

Appl. No.:

10/226802

Inventors:

Xia (Susan) Li - Fremont CA, US
Eugene A. Delenia - Morgan Hill CA, US
Rosalinda M. Ring - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/00

US Classification:

216 66, 216 75, 438712, 438725, 2504923

Abstract:

A system and method for exposing and/or milling a copper metallization layer disposed in dielectric that may have an overlying polyimide layer preferably by use of a FIB machine system used for exposing/milling aluminum metallization layers is disclosed. The method includes using a gas assisted (GAS) system for exposing a portion of a copper metal trace disposed in a dielectric and includes the step of removing a portion of the dielectric overlying the portion of the metal trace using the GAS system activated with a dielectric selective chemical that does not have a significant spontaneous (non ion-beam induced) reaction with the metal trace. The system includes a focused ion beam (FIB) machine for exposing/milling a portion of a metal trace disposed in a dielectric substrate wherein the metal trace is copper.

US Patent:

62419072, Jun 5, 2001

Filed:

Dec 9, 1998

Appl. No.:

9/208824

Inventors:

Ranjit Gannamani - Santa Clara CA
Xia Li - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B44C 122

US Classification:

216 83

Abstract:

A system and method for decapsulating a chip-scale package having a first width are disclosed. The method and system include coupling the chip-scale package to a substantially rigid receptacle. The receptacle has a second width and a periphery. The second width is larger than the first width. The chip-scale package does not extend to the periphery of the receptacle. The method and system further include holding the receptacle in proximity to the periphery and decapsulating the chip-scale package.

US Patent:

63247569, Dec 4, 2001

Filed:

Dec 9, 1998

Appl. No.:

9/208825

Inventors:

Xia Li - Fremont CA
Ranji Gannamani - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H05K 330

US Classification:

29841

Abstract:

A system and method for providing plastic ball grid array ("PBGA") packages is disclosed. In one aspect, the method and system provide a plurality of PBGA packages. Each of the plurality of PBGA packages including a semiconductor die and a portion of a substrate. The semiconductor die is electrically coupled to the portion of the substrate. The portion of the substrate has an edge. In this aspect, the method and system include forming the plurality of PBGA packages on the substrate and separating the portion of the substrate for each of the plurality of PBGA packages. The portion of the substrate for one of the plurality of PBGA packages is separated from the portion of the substrate for another of the plurality of PBGA packages by a gap. In a preferred embodiment, the gap is created by punching the substrate. The method and system further include filling the gap with a moisture sealant and cutting the moisture sealant to separate the plurality of PBGA packages.

US Patent:

61473995, Nov 14, 2000

Filed:

Sep 4, 1998

Appl. No.:

9/148666

Inventors:

Xia Li - Fremont CA
Daniel Yim - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 23053

US Classification:

257700

Abstract:

Aspects for exposing local areas for desired nodes in a multi-layer integrated circuit from the backside are described. In an exemplary method aspect, the method includes removing a predetermined portion of a first backside layer, opening chosen local areas with focused ion beam etching through at least the first backside layer, and exposing a desired node in a metal layer lower than the first backside layer with reactive ion etching. The method further includes removing the predetermined portion by performing reactive ion etching to a predetermined stop point. Alternatively, the first backside layer is mechanically polished to a predetermined thickness. Additionally, the method includes utilizing a high current ion beam during the focused ion beam etching.