Xiang Li

US Patent:

7778105, Aug 17, 2010

Filed:

Mar 17, 2008

Appl. No.:

12/049798

Inventors:

Robert T. Golla - Round Rock TX, US
Xiang Shan Li - Austin TX, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G11C 7/00
G11C 8/00

US Classification:

36523005, 36518905, 36523008, 3652331, 3652335

Abstract:

A memory with a write port configured for double-pump writes. The memory includes a first and second memory locations each having one or more bit cells, and one or more bit lines each coupled to corresponding ones of the bit cells. A write port is coupled to each of the bit lines. Selection circuitry, responsive to a first clock edge, latches first data from a first data path through the write port, and responsive to a second clock edge, latches second data from a second data path through the write port. A first pulse is generated during a first phase of the clock signal to cause writing of the first data into the first memory location. A second pulse is generated during a second phase of the clock signal to cause writing of the second data into the second memory location.

US Patent:

8458446, Jun 4, 2013

Filed:

Sep 30, 2009

Appl. No.:

12/570682

Inventors:

Christopher H. Olson - Austin TX, US
Xiang Shan Li - Austin TX, US
Robert T. Golla - Round Rock TX, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/30

US Classification:

712228

Abstract:

A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.

US Patent:

20100332804, Dec 30, 2010

Filed:

Jun 29, 2009

Appl. No.:

12/493743

Inventors:

Robert T. Golla - Round Rock TX, US
Matthew B. Smittle - Allen TX, US
Mark A. Luttrell - Cedar Park TX, US
Xiang Shan Li - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712214, 712216, 712E09016

Abstract:

Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields.

US Patent:

20100332806, Dec 30, 2010

Filed:

Jun 30, 2009

Appl. No.:

12/495025

Inventors:

Robert T. Golla - Round Rock TX, US
Matthew B. Smittle - Allen TX, US
Xiang Shan Li - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712216, 712E09028

Abstract:

Systems and methods for identification of dependent instructions on speculative load operations in a processor. A processor allocates entries of a unified pick queue for decoded and renamed instructions. Each entry of a corresponding dependency matrix is configured to store a dependency bit for each other instruction in the pick queue. The processor speculates that loads will hit in the data cache, hit in the TLB and not have a read after write (RAW) hazard. For each unresolved load, the pick queue tracks dependent instructions via dependency vectors based upon the dependency matrix. If a load speculation is found to be incorrect, dependent instructions in the pick queue are reset to allow for subsequent picking, and dependent instructions in flight are canceled. On completion of a load miss, dependent operations are re-issued. On resolution of a TLB miss or RAW hazard, the original load is replayed and dependent operations are issued again from the pick queue.

US Patent:

20210399722, Dec 23, 2021

Filed:

Jun 19, 2020

Appl. No.:

16/906501

Inventors:

- San Diego CA, US
Keith Alan BOWMAN - Morrisville NC, US
Nadeem ELEYAN - Austin TX, US
Xiang LI - Austin TX, US

International Classification:

H03K 5/133
H03L 7/081

Abstract:

Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.

US Patent:

20170346280, Nov 30, 2017

Filed:

May 27, 2016

Appl. No.:

15/166683

Inventors:

- Austin TX, US
Gregory C. EDGINGTON - Lakeway TX, US
James R. FEDDELER - Austin TX, US
Xiang LI - Austin TX, US
Richard W. MOSELEY - Austin TX, US
Mihir SUCHAK - Morrisville NC, US

International Classification:

H02H 9/04
H02H 1/00

Abstract:

An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node, and a second current electrode coupled to a data input of the latch, wherein the latch is configured to store an indication that a transient event occurred. An event level sensor includes a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to the protection device, and a second current electrode coupled to a load circuit; a rectifier device coupled between the second current electrode and a capacitor; a second transistor having a control electrode coupled to the capacitor; and an output circuit configured to place a current on a first sense bus proportional to a current through the load circuit.

US Patent:

20170173578, Jun 22, 2017

Filed:

Mar 13, 2015

Appl. No.:

15/126030

Inventors:

- Austin TX, US
Christopher Renault - Austin TX, US
Stephen E. Fosdick - Austin TX, US
Xiang Li - Austin TX, US

International Classification:

B01L 3/00
G01N 27/30
G01N 27/48
G01N 27/403
G01N 33/66
G01N 33/68

Abstract:

Provided herein are paper-based microfluidic devices that can be configured to induce fast fluid flow through a hollow microfluidic channel under low applied pressure. The microfluidic devices can comprise a fluid inlet, a fluid outlet, and a hollow channel fluidly connecting the fluid inlet and the fluid outlet, so as to form a fluid flow path from the fluid inlet to the fluid outlet. The hollow channel can comprise a fluid flow path defined by a floor, two or more side walls, and optionally a ceiling. One or more of the interior surfaces of the hollow channel can comprise a hydrophilic material. The hydrophilic material can drive fluid flow through the hollow channel, allowing for fast fluid flow through the hollow microfluidic channel under low applied pressure. The devices are well suited for use in numerous sensing applications, for example, quantitative, low limit-of-detection, and/or point-of-care paper analytical devices.

US Patent:

20160146755, May 26, 2016

Filed:

Nov 25, 2015

Appl. No.:

14/952008

Inventors:

- Austin TX, US
Long Luo - Austin TX, US
Xiang Li - Austin TX, US

International Classification:

G01N 27/447
G01N 33/487
G01N 27/416

Abstract:

Disclosed herein are devices that can be used to perform electrophoretic separations as well as methods of using thereof. The devices and methods described herein are inexpensive, user friendly, sensitive, portable, robust, efficient, thin, rapid, and use low voltage. As such, the device and methods are well suited for use in numerous applications including point-of-care (POC) diagnostics.

Address:

6636 W William Cannon Dr, Austin, TX 78735

Phone:

5732029936

VIN:

WMWSU3C56CT262398

Make:

MINI

Model:

COOPER

Year:

2012