Xiao Hong Sun

US Patent:

58587012, Jan 12, 1999

Filed:

Oct 3, 1994

Appl. No.:

8/317310

Inventors:

Morris F. White - West Roxbury MA
Xiao Jian Sun - Boston MA
Jacalyn H. Pierce - Potomac MD

Assignee:

Joslin Diabetes Center, Inc. - Boston MA

International Classification:

C12N 1512
C12N 1563
C12N 1585

US Classification:

435 691

Abstract:

A substantially pure nucleic acid comprising a sequence encoding an IRS-2 polypeptide, a substantially pure preparation of an IRS-2 polypeptide, and related methods.

US Patent:

20200265298, Aug 20, 2020

Filed:

Feb 19, 2019

Appl. No.:

16/279416

Inventors:

- Armonk NY, US
Malte Rasch - Chappaqua NY, US
Xiao Sun - Pleasantville NY, US
Yulong Li - Westchester NY, US
Zhibin Ren - Hopewell Junction NY, US

International Classification:

G06N 3/063
G06N 3/04
G06K 9/62

Abstract:

Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.

US Patent:

20200118638, Apr 16, 2020

Filed:

Oct 11, 2018

Appl. No.:

16/157848

Inventors:

- Armonk NY, US
Tayfun Gokmen - Briarcliff Manor NY, US
Xiao Sun - Yorktown Heights NY, US
Yulong Li - Hartsdale NY, US
Malte Rasch - Chappaqua NY, US

International Classification:

G11C 27/00
G06N 3/04

Abstract:

A method for multiple copies of a set of multi-kernel set operations in a hardware accelerated neural network includes a word line for receiving a pixel value of an input image. A bit line communicates a modified pixel value. An analog memory cell including a first capacitor stores a first kernel weight of a first kernel in one of a plurality of kernel sets such that the pixel value is operated on by the first kernel weight to produce the modified pixel value. A charge connection connects the first capacitor to at least a second capacitor storing a second kernel weight of a related kernel of a second one of the plurality of kernel sets such that charge is shared between the first capacitor and at least the second capacitor to normalize the first kernel weight and the second kernel weight.

US Patent:

20200058641, Feb 20, 2020

Filed:

Oct 24, 2019

Appl. No.:

16/662284

Inventors:

- Armonk NY, US
Yulong Li - Hartsdale NY, US
Dennis M. Newns - Yorktown Heights NY, US
Paul M. Solomon - Yorktown Heights NY, US
Xiao Sun - Yorktown Heights NY, US

International Classification:

H01L 27/06
H01L 29/51
H01L 29/49
H01L 29/06
H01L 27/1159
H01L 27/11507
H01L 21/28

Abstract:

A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

US Patent:

20200013785, Jan 9, 2020

Filed:

Sep 19, 2019

Appl. No.:

16/576441

Inventors:

- Armonk NY, US
Paul M. Solomon - Yorktown Heights NY, US
Xiao Sun - Yorktown Heights NY, US

International Classification:

H01L 27/1159
H01L 27/092
H01L 29/45
H01L 29/78

Abstract:

A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.

US Patent:

20200005848, Jan 2, 2020

Filed:

Jun 28, 2018

Appl. No.:

16/021575

Inventors:

- Armonk NY, US
Jin-Ping Han - Yorktown Heights NY, US
Dennis M. Newns - Yorktown Heights NY, US
Paul M. Solomon - Westchester NY, US
Xiao Sun - Yorktown Heights NY, US

International Classification:

G11C 11/22
G11C 11/54
G06F 3/06
G06N 3/063

Abstract:

A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.

US Patent:

20190378555, Dec 12, 2019

Filed:

Aug 26, 2019

Appl. No.:

16/550809

Inventors:

- Armonk NY, US
Xiao Sun - Pleasantville NY, US
Teng Yang - New York NY, US

International Classification:

G11C 11/22
H03K 19/177

Abstract:

Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

US Patent:

20190326387, Oct 24, 2019

Filed:

Jul 3, 2019

Appl. No.:

16/502783

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Xiao Sun - Pleasantville NY, US
Jin Ping Han - Yorktown Heights NY, US
Vijay Narayanan - New York NY, US

International Classification:

H01L 49/02
H01B 3/10
H01L 27/11507
H01L 21/02
H01L 21/3213
H01L 21/283

Abstract:

Artificial synaptic devices with an HfO-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400 C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.