Xiaohua Zhuang from San Mateo, CA

Us Patents

Apparatus And Method In A Network Switch For Dynamically Assigning Memory Interface Slots Between Gigabit Port And Expansion Port
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US Patent:

6501734, Dec 31, 2002
Filed:

May 24, 1999
Appl. No.:

09/317150
Inventors:

Ching Yu - Santa Clara CA
Xiaohua Zhuang - Santa Clara CA
Bahadir Erimli - Campbell CA
John M. Chiang - San Jose CA
Shashank Merchant - Sunnyvale CA
Robert Williams - Cupertino CA
Edward Yang - San Jose CA
Chandan Egbert - San Jose CA
Vallath Nandakumar - Campbell CA
Ian Lam - Daly City CA
Eric Tsin-Ho Leung - San Jose CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H04J 116
US Classification:

370236, 370230, 370235, 370237
Abstract:

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802. 3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.

Method And Apparatus For Reclaiming Buffers Using A Single Buffer Bit
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US Patent:

6504846, Jan 7, 2003
Filed:

May 21, 1999
Appl. No.:

09/315724
Inventors:

Ching Yu - Santa Clara CA
Xiaohua Zhuang - Santa Clara CA
Bahadir Erimli - Campbell CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H04L 1256
US Classification:

370412, 3703957
Abstract:

A method and apparatus are disclosed for reclaiming frame buffers used to store data frames received by a network switch. The apparatus includes a multicopy queue for queuing entries corresponding to received data frames which must be transmitted by multiple output ports of the network switch, a free buffer queue for queuing frame pointers that identify locations in an external memory where reclaimed frame buffers are located, and a multicopy circuit that retrieves entries from the multicopy queue and determines if all copies of a received data frame have been transmitted by the specified output ports. The multicopy circuit also reclaims one or more frame buffers, based on the size of the received data frame. The present invention allows efficient reclaiming of frame buffers regardless of whether the received data frame is stored in a single frame buffer or multiple frame buffers.

Arrangement Determining Policies For Layer 3 Frame Fragments In A Network Switch
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US Patent:

6798788, Sep 28, 2004
Filed:

Jan 14, 2000
Appl. No.:

09/482957
Inventors:

Somnath Viswanath - Sunnyvale CA
Mrudula Kanuri - Santa Clara CA
Xiaohua Zhuang - Santa Clara CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H04L 1256
US Classification:

370469
Abstract:

A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802. 3) network without blocking of incoming data packets, includes network switch ports, each including a policy filter configured for obtaining layer 3 and layer 4 information from a received layer 2 frame. The layer 3 information and the layer 4 information is used to determine a policy identifier that specifies a layer 3 switching operation to be performed on the received layer 2 frame. Each network switch port also includes a flow identification module that caches portions of the layer 3 information and the corresponding policy identifier. The cached portions of the layer 3 information and the corresponding policy identifier are then used by the flow identification module to identify the appropriate policy for subsequent fragmented layer 3 frames that lack the layer 4 information necessary for performing another policy lookup, but that have sufficient layer 3 information to uniquely identify each layer three flow. Hence, each layer 3 fragment can be assigned a unique policy for execution of layer 3 switching decisions.

Apparatus And Method For Programmable Memory Access Slot Assignment
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US Patent:

7031305, Apr 18, 2006
Filed:

May 24, 1999
Appl. No.:

09/317156
Inventors:

Ching Yu - Santa Clara CA, US
Xiaohua Zhuang - Santa Clara CA, US
Bahadir Erimli - Campbell CA, US
John M. Chiang - San Jose CA, US
Shashank Merchant - Sunnyvale CA, US
Robert Williams - Cupertino CA, US
Edward Yang - San Jose CA, US
Chandan Egbert - San Jose CA, US
Vallath Nandakumar - Campbell CA, US
Ian Lam - Daly City CA, US
Eric Tsin-Ho Leung - San Jose CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H04L 12/28
US Classification:

370389, 3703954, 370412, 370458, 370468
Abstract:

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802. 3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

Arrangement In A Network Switch For Prioritizing Data Frames Based On User-Defined Frame Attributes
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US Patent:

7502366, Mar 10, 2009
Filed:

May 23, 2000
Appl. No.:

09/576021
Inventors:

Bahadir Erimli - Campbell CA, US
Gopal S. Krishna - San Jose CA, US
Chandan Egbert - San Jose CA, US
Peter Ka-Fai Chow - San Jose CA, US
Mrudula Kanuri - Santa Clara CA, US
Shr-Jie Tzeng - Fremont CA, US
Somnath Viswanath - Sunnyvale CA, US
Xiaohua Zhuang - Santa Clara CA, US
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H04L 12/28
US Classification:

370389
Abstract:

A network switch includes network switch ports, each including a port filter configured for detecting user-selected attributes from a received layer 2 type data frame. Each port filter, upon detecting a user-selected attribute in a received layer 2 type data frame, sends a signal to a switching module indicating the determined presence of the user-selected attribute, enabling the switching module to generate a switching decision based on the corresponding user-selected attribute and based on a corresponding user-defined switching policy. The switching policy may specify a priority class, or a guaranteed quality of service (e. g. , a guaranteed bandwidth), ensuring that the received layer 2 type data frame receives the appropriate switching support. The user-selected attributes for the port filter and the user-defined switching policy for the switching module are programmed by a host processor. Hence, the integrated network switch is able to perform advanced switching operations for layer 2 type data packets to ensure quality of service requirements, independent of priority information specified in the layer 2 type data packets, based on the user-selected attributes in the layer 2 type data packets and the user-defined switching policies established for the switching module.

Apparatus And Method In A Network Switch For Swapping Memory Access Slots Between Gigabit Port And Expansion Port
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US Patent:

6442137, Aug 27, 2002
Filed:

May 24, 1999
Appl. No.:

09/317143
Inventors:

Ching Yu - Santa Clara CA
Xiaohua Zhuang - Santa Clara CA
Bahadir Erimli - Campbell CA
John M. Chiang - San Jose CA
Shashank Merchant - Sunnyvale CA
Robert Williams - Cupertino CA
Edward Yang - San Jose CA
Chandan Egbert - San Jose CA
Vallath Nandakumar - Campbell CA
Ian Lam - Daly City CA
Eric Tsin-Ho Leung - San Jose CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H04L 522
US Classification:

370232, 370468, 370229, 370429, 710310, 710311
Abstract:

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802. 3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.