Xiaojun Zhu

US Patent:

7385861, Jun 10, 2008

Filed:

Aug 18, 2006

Appl. No.:

11/465514

Inventors:

Xiaojun Zhu - Milpitas CA, US

Assignee:

Ambarella, Inc. - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365194, 3652331, 36523311

Abstract:

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first strobe signal having an unknown phase in relation to a local clock signal when receiving data from a memory. The second circuit may be configured to synchronize the first strobe signal with the local clock signal by (i) generating one or more second strobe signals and (ii) inserting a predetermined cycle delay between the one or more second strobe signals and the local clock signal.

US Patent:

7613756, Nov 3, 2009

Filed:

Jan 11, 2005

Appl. No.:

11/034074

Inventors:

Xiaojun Zhu - Milpitas CA, US
Reading G. Maley - San Francisco CA, US
Sompur M. Shivakumar - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 7/58

US Classification:

708250, 708251

Abstract:

An apparatus and a method are provided for generating a random number, wherein the randomness of the random number is derived from thermal noise present across a pair of resistors. Each of the pair of resistors is defined to receive a respective input voltage and add a respective noise component to the input voltage. The output from each resistor in the pair of resistors is amplified to generate a noisy analog voltage that includes a representation of the random noise components added by the pair of resistors. The randomly varying noisy analog voltage is used to control a voltage controlled oscillator (VCO). The VCO generates a random digital signal based on the randomly varying noisy analog voltage. The random digital signal generated by the VCO is used to set a number of bits for defining a random number.

US Patent:

8334715, Dec 18, 2012

Filed:

Jun 10, 2011

Appl. No.:

13/157488

Inventors:

Harish S. Muthali - San Jose CA, US
Xiaojun Zhu - Saratoga CA, US

Assignee:

Ambarella, Inc. - Santa Clara CA

International Classification:

H03K 5/12

US Classification:

327170, 327172, 327175, 327276, 326 46

Abstract:

An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.

US Patent:

7161402, Jan 9, 2007

Filed:

May 13, 2005

Appl. No.:

11/129681

Inventors:

Shivakumar Sompur - Sunnyvale CA, US
Xiaojun Zhu - Milpitas CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H03L 7/06

US Classification:

327158, 327161

Abstract:

A delay lock loop (DLL) system includes a master DLL and at least one slave DLL. The master DLL comprises a master delay line, a phase detector, and a loop controller. The master delay line of the master DLL includes four quarter cycle delay lines (QCDL). The slave DLL comprises a delay line and a fractional bit delay element. The delay line of the slave DLL is controlled by the slave delay line control signal generated by the loop controller of the master DLL. The final output of the slave DLL is formed such that the output of the delay line of the slave DLL is corrected by the fractional bit delay generated by the factional bit delay element such that the final output of the slave DLL has a finer delay line resolution than the one of the output of the delay line of the slave DLL.