Xiaonan Chen from San Diego, CA, age 45

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Location:

4873 Carriage Run Dr, San Diego, CA 92130

Industry:

Semiconductors

Work:

Micron Technology
Engineer

Education:

Nanyang Technological University
Bachelors, Business, Accounting, Actuarial Science

Skills:

Semiconductors
Device Characterization
Thin Films
Characterization
Ic
Simulations
Matlab
Cmos
Design of Experiments
Silicon

Languages:

English

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Variable Resistance Memory Programming
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US Patent:

8446758, May 21, 2013
Filed:

Dec 14, 2010
Appl. No.:

12/967592
Inventors:

Xiaonan Chen - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

G11C 11/00
US Classification:

365163, 364148
Abstract:

Some embodiments include a device having memory elements and methods of storing information into the memory elements. Such methods can include increasing a temperature of a portion of a memory element for a time interval during an operation to change a resistance state of the memory element. After the time interval, the methods can include decreasing the temperature of the portion of the memory element. Decreasing the temperature can be performed using a signal having a first negative slope and a second negative slope. Other embodiments are described.

Multimode Interference Coupler For Use With Slot Photonic Crystal Waveguides
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US Patent:

20100226608, Sep 9, 2010
Filed:

Aug 28, 2009
Appl. No.:

12/550186
Inventors:

Xiaonan Chen - Austin TX, US
Ray T. Chen - Austin TX, US
Assignee:

Board of Regents, The University of Texas System - Austin TX
International Classification:

G02B 6/26
US Classification:

385 28, 264 125
Abstract:

The present invention provides an optical apparatus having a multimode interference coupler configured to optically couple a strip waveguide to a slot photonic crystal waveguide. The multimode interference coupler has a coupling efficiency to the slot photonic crystal waveguide greater than or equal to 90%, a width that is approximately equal to a defect width of the slot photonic crystal waveguide, a length that is equal to or less than 1.5 μm, and interfaces with the slot photonic crystal waveguide at an edge of a period that gives a termination parameter of approximately zero. The optical apparatus may also include an insulation gap disposed between the multimode interference coupler and the slot photonic crystal waveguide, wherein the length of the multimode interference coupler is reduced by approximately one half of a width of the insulation gap.

Stabilization Of Resistive Memory
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US Patent:

20130094275, Apr 18, 2013
Filed:

Oct 18, 2011
Appl. No.:

13/275901
Inventors:

Xiaonan Chen - Boise ID, US
Assignee:

MICRON TECHNOLOGY, INC. - Boise ID
International Classification:

G11C 11/00
US Classification:

365148
Abstract:

The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming signal to a resistive memory cell, wherein the programming signal includes a first portion having a first polarity and a second portion having a second polarity, wherein the second polarity is opposite the first polarity.

Performing Forming Processes On Resistive Memory
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US Patent:

20130107605, May 2, 2013
Filed:

Nov 1, 2011
Appl. No.:

13/286375
Inventors:

Xiaonan Chen - Boise ID, US
Assignee:

MICRON TECHNOLOGY, INC. - Boise ID
International Classification:

G11C 11/00
H05K 13/00
US Classification:

365148, 295921
Abstract:

The present disclosure includes apparatuses and methods for performing forming processes on resistive memory. A number of embodiments include applying a formation signal to the storage element of a resistive memory cell, wherein the formation signal includes a first portion having a first polarity and a first amplitude, a second portion having a second polarity and a second amplitude, wherein the second polarity is opposite the first polarity and the second amplitude is smaller than the first amplitude, and a third portion having the first polarity and a third amplitude that is smaller than the first amplitude.

Systems, And Devices, And Methods For Programming A Resistive Memory Cell
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US Patent:

20130223163, Aug 29, 2013
Filed:

Feb 28, 2012
Appl. No.:

13/407007
Inventors:

Xiaonan Chen - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

G11C 7/00
US Classification:

365189011
Abstract:

Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions.

Variable Resistance Memory Programming
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US Patent:

20130258754, Oct 3, 2013
Filed:

May 17, 2013
Appl. No.:

13/897040
Inventors:

Xiaonan Chen - Boise ID, US
Assignee:

Micron Technology, Inc. - Boise ID
International Classification:

G11C 13/00
US Classification:

365148
Abstract:

Some embodiments include a device having memory elements and methods of storing information into the memory elements. Such methods can include increasing a temperature of a portion of a memory element for a time interval during an operation to change a resistance state of the memory element. After the time interval, the methods can include decreasing the temperature of the portion of the memory element. Decreasing the temperature can be performed using a signal having a first negative slope and a second negative slope. Other embodiments are described.

Methods Of Forming Resistive Memory Elements And Related Resistive Memory Elements, Resistive Memory Cells, And Resistive Memory Devices
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US Patent:

20130334483, Dec 19, 2013
Filed:

Jun 14, 2012
Appl. No.:

13/523356
Inventors:

D. V. Nirmal Ramaswamy - Boise ID, US
Sanh D. Tang - Boise ID, US
Alessandro Torsi - Boise ID, US
Muralikrishnan Balakrishnan - Boise ID, US
Xiaonan Chen - Boise ID, US
John K. Zahurak - Eagle ID, US
Assignee:

MICRON TECHNOLOGY, INC. - Boise ID
International Classification:

H01L 47/00
H01L 21/02
US Classification:

257 2, 438382, 257E47001, 257E21004
Abstract:

A method of forming a resistive memory element comprises forming an oxide material over a first electrode. The oxide material is exposed to a plasma process to form a treated oxide material. A second electrode is formed on the treated oxide material. Additional methods of forming a resistive memory element, as well as related resistive memory elements, resistive memory cells, and resistive memory devices are also described.

Compute-In-Memory Bitcell With Capacitively-Coupled Write Operation
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US Patent:

20220230679, Jul 21, 2022
Filed:

Jan 19, 2021
Appl. No.:

17/152564
Inventors:

- San Diego CA, US
Xiaonan CHEN - San Diego CA, US
Ankit SRIVASTAVA - San Diego CA, US
Sameer WADHWA - San Diego CA, US
Zhongze WANG - San Diego CA, US
International Classification:

G11C 11/419
G06F 7/544
Abstract:

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.