Xiaoyao Liang

age ~55

from Cupertino, CA

Also known as:
  • Liang Xiaoyao

Xiaoyao Liang Phones & Addresses

  • Cupertino, CA
  • Sunnyvale, CA
  • Hillsboro, OR
  • Malden, MA
  • Cambridge, MA
  • Stony Brook, NY
  • Roxbury Crossing, MA
  • Santa Clara, CA

Resumes

Xiaoyao Liang Photo 1

Xiaoyao Liang

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Xiaoyao Liang Photo 2

Professor At Shanghai Jiao Tong University

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Position:
Professor at Shanghai Jiao Tong University
Location:
Shanghai City, China
Industry:
Computer Hardware
Work:
Shanghai Jiao Tong University since Apr 2012
Professor

NVIDIA Nov 2008 - Apr 2012
Senior Architecture/ASIC engineer
Education:
Harvard University 2005 - 2008
Ph. D, Computer Architecture, VLSI, IC Design
State University of New York at Stony Brook 2003 - 2004
Master, Computer architecture
Fudan University 1996 - 2000
Bachelor, EE
Skills:
ASIC
Verilog
Computer Architecture
VLSI
SoC

Us Patents

  • Process Variation Tolerant Circuit With Voltage Interpolation And Variable Latency

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  • US Patent:
    20090134707, May 28, 2009
  • Filed:
    Oct 30, 2008
  • Appl. No.:
    12/261771
  • Inventors:
    Xiaoyao Liang - Cambridge MA, US
    David Brooks - Cambridge MA, US
  • International Classification:
    H02J 1/00
  • US Classification:
    307 80
  • Abstract:
    A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits. The first voltage differs from the second voltage and the plurality of pipelined stages interpolates between the first and second voltages to provide differing effective voltages between the first and second voltages.

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