Jul 2010 to Sep 2010 CE EngineerXizi-Otis Hangzhou, CN Apr 2010 to Jun 2010 Field EngineerDrexel University Philadelphia, PA School Research
Education:
Drexel University Philadelphia, PA 2014 to 2015 Master of Science in Computer EngineeringDrexel University Philadelphia, PA 2012 to 2014 Master of Science in Electrical EngineeringDrexel University Philadelphia, PA 2008 to 2012 Bachelor of Science in Electrical Engineering
Skills:
Computer skills : Microsoft Office/Linux/MATLAB/LabVIEW//P... programming/CUDA/AutoCAD/C++/V... Independent research and analysis ability Integrate basic electrical circuit boards, PCBs for ADC and DAC Layout and schematic designs for Analog and Digital and IC design AC/DC Power flow analysis, transmission, distribution and power electronics design Transient stability analysis and protective relaying
1990 to 1990 SupervisorDept of Microbiology Minneapolis, MN Sep 1986 to Sep 1989 GRADUATE RESEARCH ASSISTANTSCHOOL OF MEDICINE UNIVERSITY OF MINNESOTA Minneapolis-Saint Paul, MN Aug 1987 to Aug 1988 Graduate StudentHYBRIDOMA CELLS AND PURIFICATION OF ANTIBODIES
May 1985 to Jun 1986 GRADUATE RESEARCH ASSISTANTMEDICAL TRAINING COLLEGE IN CHINA
Mar 1984 to Mar 1985 COURSE INSTRUCTOR OF MEDICAL MICROBIOLOGY
Education:
SCHOOL OF MEDICINE Apr 1999 M.D.SCHOOL OF MEDICINE UNIVERSITY OF MINNESOTA Philadelphia, PA Aug 1978 to Aug 1983 M.S. in MICROBIOLOGY
Jun 2014 to 2000 Cashier/HostDREXEL UNIVERSITY Philadelphia, PA Sep 2012 to Jun 2013 SENIOR PROJECTDREXEL UNIVERSITY, MOLECULAR BIOLOGY LABORATORY Philadelphia, PA Sep 2012 to Dec 2012 StudentDREXEL UNIVERSITY Philadelphia, PA Apr 2012 to Sep 2012 Research Assistant Co-opBIOMECHANICS LABORATORY Philadelphia, PA Mar 2011 to Jun 2011 StudentFIRST WOK CHINESE RESTAURANT Millsboro, DE 2002 to 2010 Manager/Cashier
Mustafa Celik - Santa Clara CA, US Jiayong Le - Mountain View CA, US Lawrence Pileggi - Pittsburgh PA, US Xin Li - Pittsburgh PA, US
International Classification:
G06F 17/50 G06F 7/60 G06F 7/52
US Classification:
716 6, 716 4, 716 5, 703 2, 708607
Abstract:
The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (). Significant research has been recently focused on developing new statistical timing analysis algorithms (), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric () to assess the criticality of each path and/or arc in the statistical timing graph (). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability () is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.
Analog And Radio Frequency (Rf) System-Level Simulation Using Frequency Relaxation
Xin Li - Pittsburgh PA, US Yang Xu - San Diego CA, US Peng Li - College Station TX, US
Assignee:
Carnegie Mellon University - Pittsburgh PA
International Classification:
G06F 17/50
US Classification:
703 14, 703 4
Abstract:
Analog and radio frequency system-level simulation using frequency relaxation. Embodiments of the invention use a frequency relaxation approach for analog/RF system-level simulation that accommodates both large system size and complex signal space. The simulator can determine an output response for a system by partitioning the system into blocks and simulating the propagation of an input signal through the blocks. The input signal can take various forms, including a multi-tone sinusoidal signal, a continuous spectra signal, and/or a stochastic signal. Frequency relaxation is applied to produce individual responses. The output response can be computed based on obtaining convergence of the individual responses. The input to embodiments of the simulator can be a circuit netlist, or a block-level macromodel.
Statistical Optimization And Design Method For Analog And Digital Circuits
Xin Li - Pittsburgh PA, US Larry Pileggi - Pittsburgh PA, US
Assignee:
Xigmix, Inc. - Pittsburgh PA
International Classification:
G06F 17/50 G06F 9/45
US Classification:
716 2, 716 5
Abstract:
A computer implemented method of performing projection based polynomial fitting. The method includes generating a plurality of sampling points as a function of variables. The method also includes forming a polynomial model template representative of the plurality of sampling points. According to embodiments of the present invention, the polynomial model template comprises at least one polynomial coefficient. The method further includes forming a low-rank matrix to approximate the polynomial coefficient.
Crossbar Diode-Switched Magnetoresistive Random Access Memory System
Jian-Gang Zhu - Pittsburgh PA, US Yi Luo - Pittsburgh PA, US Xin Li - Pittsburgh PA, US
Assignee:
Carnegie Mellon University - Pittsburgh PA
International Classification:
G11C 11/14
US Classification:
365171, 365173, 365158, 365 55, 365130
Abstract:
A magnetic memory or MRAM memory system comprising an M×N crossbar array of MRAM cells. Each memory cell stores binary data bits with switchable magnetoresistive tunnel junctions (MJT) where the electrical conductance changes as the magnetic moment of one electrode (the storage layer) in the MJT switches direction. The switching of the magnetic moment is assisted by a phase transition interlayer that transitions from antiferromagnetic to ferromagnetic at a well defined, above ambient temperature.
Method For Parameterized Model Order Reduction Of Integrated Circuit Interconnects
The present invention is a method and apparatus for creating a reduced-order IC interconnect model, which incorporates variations in interconnect process parameters, and models both on-chip and off-chip interconnects. The method is based on mathematically representing an IC interconnect system, including mathematical interconnect process parameter terms, which are manipulated to facilitate simplification of an IC interconnect model. The IC interconnect model is then simplified by using a mathematical technique called state-space projection. Specifically, an IC interconnect system is represented with at least one modified nodal analysis equation (MNA) that is based on frequency, interconnect process parameters are added and substituted back into the MNA(s), terms with interconnect process parameters are explicitly matched. A state-space projection is created, which implicitly matches frequency terms. The state-space projection is used to create the reduced-order IC interconnect model.
Tunable Integrated Circuit Design For Nano-Scale Technologies
The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.
Active Resistors For Reduction Of Transient Power Grid Noise
Gokce Keskin - Pittsburgh PA, US Xin Li - Pittsburgh PA, US Lawrence Pileggi - Pittsburgh PA, US
International Classification:
H02H 7/10
US Classification:
363050000
Abstract:
Active resistors for reduction of transient power grid noise. An active resistance added in parallel to the operating circuit blocks of a semiconductor device. This resistance increases the damping ratio of the power grid, which in turn decreases the number and the magnitude of oscillations and/or noise resulting from step disturbances of the power supply current. The active resistance can implemented by a transistor connected to a bias voltage. Alternatively, the active resistance can be implemented by a drive transistor with a gain stage, or two active resistors where one responds to overshoots in the current flow and the second active resistor responds to droops in the current flow.
The present disclosure relates to tricyclic heterocycles, and pharmaceutical compositions of the same, that are inhibitors of the FGFR enzyme and are useful in the treatment of FGFR-associated diseases such as cancer.
Xin LI (2000-2004), Becca Hein (2000-2004), Alexandra Hoisington (1999-2003), Alex Flores (2003-2007)
Googleplus
Xin Li
Lived:
San Jose, CA Mountain View, CA Rochester, NY Tianjin, China Beijing, China Highland Park, NJ Pittsburgh, PA Redmond, WA
Work:
Google - Software Engineer (2010) Google - Intern Seagate - Intern Ask.com - Intern
Bragging Rights:
Never walked out of a casino, losing.
Xin Li
Lived:
Philadelphia, Pennsylvania, USA Xiangfan, PRC Wuhan, PRC Philadelphia, PA, USA
Education:
Temple University - Computer and Information Science, University at Buffalo, The State University of New York - Computer Science, Wuhan University - Software Engineering, Xiangfan No.5 High School - Science
Relationship:
Its_complicated
About:
Depart today to grow in wisdom/Return tomorrow to better serve my country and my kind!
Tagline:
Busy.....
Xin Li
Work:
Google - Senior Software Engineer (2009) IBM - Staff Software Engineer (2003-2009)
Education:
Stanford University - MS CS - Human Computer Interaction, University of Illinois at Urbana-Champaign - BA CS