Xin Lin

US Patent:

6531193, Mar 11, 2003

Filed:

Dec 11, 2000

Appl. No.:

09/734232

Inventors:

Stephen J. Fonash - State College PA
Xin Lin - Chandler AZ
Douglas M. Reber - Austin TX

Assignee:

The Penn State Research Foundation - University Park PA

International Classification:

C23C 1640

US Classification:

427579, 427162, 427167, 42725537

Abstract:

Silicon dioxide thin film have been deposited at temperatures from 25Â C. to 250Â C. by plasma enhanced chemical vapor deposition (PECVD) using tetramethylsilane (TMS) as the silicon containing precursor. At these temperatures, the PETMS oxide films have been found to exhibit adjustable stress and adjustable conformality. Post deposition annealing in forming gas at or below the deposition temperatures has been shown to be very effective in improving the PETMS oxide properties while preserving the low temperature aspect of the PETMS oxides.

US Patent:

6787858, Sep 7, 2004

Filed:

Oct 16, 2002

Appl. No.:

10/272336

Inventors:

Moaniss Zitouni - Gilbert AZ
Edouard D. de Frésart - Tempe AZ
Richard J. De Souza - Tempe AZ
Xin Lin - Phoenix AZ
Jennifer H. Morrison - Chandler AZ
Patrice Parris - Phoenix AZ

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 2994

US Classification:

257372, 257376, 257373

Abstract:

A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

US Patent:

6828650, Dec 7, 2004

Filed:

May 31, 2002

Appl. No.:

10/160940

Inventors:

Patrice Parris - Phoenix AZ
Richard J De Souza - Tempe AZ
Jennifer H. Morrison - Chandler AZ
Moaniss Zitouni - Gilbert AZ
Xin Lin - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2900

US Classification:

257518, 257378, 257514, 257565

Abstract:

A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

US Patent:

7211477, May 1, 2007

Filed:

May 6, 2005

Appl. No.:

11/124469

Inventors:

Edouard D. de Frésart - Tempe AZ, US
Richard J. De Souza - Tempe AZ, US
Xin Lin - Phoenix AZ, US
Jennifer H. Morrison - Chandler AZ, US
Patrice M. Parris - Phoenix AZ, US
Moaniss Zitouni - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438197, 438223, 438301

Abstract:

Methods and apparatus are provided for a MOSFET () exhibiting increased source-drain breakdown voltage (BVdss). Source (S) () and drain (D) () are spaced apart by a channel () underlying a gate () and one or more carrier drift spaces (′) serially located between the channel () and the source (′) or drain (′). A buried region (′) of the same conductivity type as the drift space (′) and the source (′) or drain (′) is provided below the drift space (′), separated therefrom in depth by a narrow gap (′) and ohmically coupled to the source (′) or drain (′). Current flow () through the drift space produces a potential difference (Vt) across this gap (′). As the S-D voltage (Vo) and current (, Io) increase, this difference (Vt) induces high field conduction between the drift space (′) and the buried region (′) and diverts part (, It) of the S-D current (, Io) through the buried region (′) and away from the near surface portions of the drift space (′) where breakdown generally occurs. Thus, BVdss is increased.

US Patent:

7301187, Nov 27, 2007

Filed:

Mar 21, 2007

Appl. No.:

11/689313

Inventors:

Edouard D. Defresart - Tempe AZ, US
Richard J. Desouza - Tempe AZ, US
Xin Lin - Phoenix AZ, US
Jennifer H. Morrison - Chandler AZ, US
Patrice M. Parris - Phoenix AZ, US
Moaniss Zitouni - Gilbert AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257288, 257341, 257401, 257E2913

Abstract:

Methods and apparatus are provided for a MOSFET () exhibiting increased source-drain breakdown voltage (BVdss). Source (S) () and drain (D) () are spaced apart by a channel () underlying a gate () and one or more carrier drift spaces (′) serially located between the channel () and the source (′) or drain (′). A buried region (′) of the same conductivity type as the drift space (′) and the source (′) or drain (′) is provided below the drift space (′), separated therefrom in depth by a narrow gap (′) and ohmically coupled to the source (′) or drain (′). Current flow () through the drift space produces a potential difference (Vt) across this gap (′). As the S-D voltage (Vo) and current (, Io) increase, this difference (Vt) induces high field conduction between the drift space (′) and the buried region (′) and diverts part (, It) of the S-D current (, Io) through the buried region (′) and away from the near surface portions of the drift space (′) where breakdown generally occurs. Thus, BVdss is increased.

US Patent:

7910441, Mar 22, 2011

Filed:

Jul 19, 2006

Appl. No.:

11/489793

Inventors:

Hongning Yang - Chandler AZ, US
Xin Lin - Phoenix AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/8234

US Classification:

438275, 438202, 438276, 438279, 438283

Abstract:

A semiconductor device includes a substrate (), a source region () formed over the substrate, a drain region () formed over the substrate, a first gate electrode () over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode () over the substrate adjacent to the drain region and between the source and drain regions.

US Patent:

7915704, Mar 29, 2011

Filed:

Jan 26, 2009

Appl. No.:

12/359845

Inventors:

Xin Lin - Phoenix AZ, US
Daniel J. Blomberg - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/872

US Classification:

257476, 257281, 257E29271, 438167

Abstract:

Improved Schottky diodes () with reduced leakage current and improved breakdown voltage are provided by building a JFET () into the diode, serially located in the anode-cathode current path (). The gates of the JFET () formed by doped regions () placed above and below the diode's current path () are coupled to the anode () of the diode (), and the current path () passes through the channel region () of the JFET (). Operation is automatic so that as the reverse voltage increases, the JFET () channel region () pinches off, thereby limiting the leakage current and clamping the voltage across the Schottky junction () at a level below the Schottky junction () breakdown. Increased reverse voltage can be safely applied until the device eventually breaks down elsewhere. The impact on device area and area efficiency is minimal and the device can be built using a standard fabrication process so that it can be easily integrated into complex ICs.

US Patent:

7927955, Apr 19, 2011

Filed:

Jun 19, 2008

Appl. No.:

12/142115

Inventors:

Xin Lin - Phoenix AZ, US
Bernhard H. Grote - Phoenix AZ, US
Hongning Yang - Chandler AZ, US
Jiang-Kai Zuo - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/331

US Classification:

438309, 438371, 438377, 257E27053

Abstract:

By providing a novel bipolar device design implementation, a standard CMOS process (-) can be used unchanged to fabricate useful bipolar transistors () and other bipolar devices having adjustable properties by partially blocking the P or N well doping () used for the transistor base (). This provides a hump-shaped base () region with an adjustable base width (), thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process (-) alone. By further partially blocking the source/drain doping step () used to form the emitter () of the bipolar transistor (), the emitter shape and effective base width () can be further varied to provide additional control over the bipolar device () properties. The embodiments thus include prescribed modifications to the masks () associated with the bipolar device () that are configured to obtain desired device properties. The CMOS process steps (-) and flow are otherwise unaltered and no additional process steps are required.