Yan Y Lin

US Patent:

20050172252, Aug 4, 2005

Filed:

Nov 1, 2004

Appl. No.:

10/979868

Inventors:

Chih-Liang Cheng - Fremont CA, US
Yan Lin - Fremont CA, US
Kuo-Feng Liao - Saratoga CA, US

Assignee:

Mentor Graphics Corp. - Wilsonville OR

International Classification:

G06F017/50

US Classification:

716010000, 716008000

Abstract:

A tool that a user may employ to assemble the components of a circuit in a floor plan design. The tool provides a user interface that displays the placement of blocks in a floor plan design, and the routing of wires among the blocks. When the designer moves the placement of a target block, the user interface automatically moves any adjacent blocks that would impede the movement of the target block and any block that would impede a block moved in response to the movement of the target block. The user interface may also respond to movement of a target block by showing how various features of the circuit will change as a result of the move. Thus, the user interface may show that moving one block closer to another block will create undesired wiring congestion in the circuit. The user interface also may show when moving a block will result in wiring connections that are too long to maintain a desired voltage level. The tool may also automatically move the placement of related blocks as a group, so that various attributes, such as a minimum distance between adjacent blocks, are maintained.

US Patent:

20060076547, Apr 13, 2006

Filed:

Sep 26, 2005

Appl. No.:

11/236424

Inventors:

Yan Lin - Fremont CA, US
Tsubomi Imamura - San Jose CA, US

Assignee:

Mentor Graphics Corp. - Wilsonville OR

International Classification:

H01L 47/00
H01L 29/00

US Classification:

257001000

Abstract:

An editing tool that provides a user interface for displaying and editing a representation of a microcircuit design. More particularly, the user interface displays a three dimensional representation of a second portion of the circuit design. A user can then select and edit a structure employing the three-dimensional representation of the structure in the user interface.

US Patent:

20120010125, Jan 12, 2012

Filed:

Apr 19, 2011

Appl. No.:

13/066620

Inventors:

Eric A. Stone - Chappaqua NY, US
Yan Lin - Jersey City NJ, US
David Quartermain - New York NY, US
Yasmeen Sarfraz - Jackson Heights NY, US

International Classification:

A61K 31/24
A61K 31/664
A61K 38/05
A61K 38/06
A61K 31/517
A61P 25/22
A61K 31/403
A61K 31/417
A61K 31/4985
A61P 25/24
A61P 25/00
A61K 31/685
A61K 31/454

US Classification:

514 13, 514548, 514118, 51425217, 514323, 514411, 514401, 514250

Abstract:

Compounds and pharmaceutical compositions containing such compounds having formula I are provided:where R, R, R, R, R, and Rare as defined herein. The compounds and pharmaceutical compositions thereof are useful for the prevention and treatment of a variety of conditions in mammals including humans, including anxiety and mood disorders such as depression.

US Patent:

20150178645, Jun 25, 2015

Filed:

Aug 6, 2014

Appl. No.:

14/452946

Inventors:

- Short Hills NJ, US
Yan LIN - New Providence NJ, US
Paul Douglas BALLEW - Madison NJ, US
Nipa BASU - Bridgewater NJ, US
Anjali REDDI - Martinsville NJ, US
Robin Fry DAVIES - Macungie PA, US
Alla KRAMSKAIA - Edison NJ, US
Brian Scott CRIGLER - Westfield NJ, US
Guang YANG - Short Hills, CN

International Classification:

G06Q 10/06

Abstract:

There is provided a method that includes (a) examining records that describe transactions between entities, (b) constructing, in a database, a data structure that represents a relationship network, based on the transactions, where the relationship network represents (i) a first entity and (ii) a second entity that is separated from the first entity by N tiers, and where N is a whole number greater than or equal to 1, and (c) calculating a relevance of the second entity to the first entity as a function of, i.e., based on, a characteristic of the second entity. There is also provided a system that performs the method, and a storage medium that contains instructions for controlling a processor to perform the method.