Yan Q Lin

US Patent:

7984397, Jul 19, 2011

Filed:

Jan 23, 2009

Appl. No.:

12/359091

Inventors:

Yan Lin - Sunnyvale CA, US
Yi-Min Jiang - San Jose CA, US
Lin Yuan - Mountain View CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716100

Abstract:

A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i. e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

US Patent:

20050172252, Aug 4, 2005

Filed:

Nov 1, 2004

Appl. No.:

10/979868

Inventors:

Chih-Liang Cheng - Fremont CA, US
Yan Lin - Fremont CA, US
Kuo-Feng Liao - Saratoga CA, US

Assignee:

Mentor Graphics Corp. - Wilsonville OR

International Classification:

G06F017/50

US Classification:

716010000, 716008000

Abstract:

A tool that a user may employ to assemble the components of a circuit in a floor plan design. The tool provides a user interface that displays the placement of blocks in a floor plan design, and the routing of wires among the blocks. When the designer moves the placement of a target block, the user interface automatically moves any adjacent blocks that would impede the movement of the target block and any block that would impede a block moved in response to the movement of the target block. The user interface may also respond to movement of a target block by showing how various features of the circuit will change as a result of the move. Thus, the user interface may show that moving one block closer to another block will create undesired wiring congestion in the circuit. The user interface also may show when moving a block will result in wiring connections that are too long to maintain a desired voltage level. The tool may also automatically move the placement of related blocks as a group, so that various attributes, such as a minimum distance between adjacent blocks, are maintained.

US Patent:

20060076547, Apr 13, 2006

Filed:

Sep 26, 2005

Appl. No.:

11/236424

Inventors:

Yan Lin - Fremont CA, US
Tsubomi Imamura - San Jose CA, US

Assignee:

Mentor Graphics Corp. - Wilsonville OR

International Classification:

H01L 47/00
H01L 29/00

US Classification:

257001000

Abstract:

An editing tool that provides a user interface for displaying and editing a representation of a microcircuit design. More particularly, the user interface displays a three dimensional representation of a second portion of the circuit design. A user can then select and edit a structure employing the three-dimensional representation of the structure in the user interface.

US Patent:

7469394, Dec 23, 2008

Filed:

Aug 9, 2006

Appl. No.:

11/502320

Inventors:

Michael D. Hutton - Mountain View CA, US
Yan Lin - Los Angeles CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 6, 716 5, 716 18

Abstract:

Design compilation software uses statistical analysis techniques to account for variations in device attributes. A compilation phase determines statistical attributes of edges and other elements of device, such as the mean and variance values of attributes. A compilation phase evaluates the suitability of a potential configuration of the device using a cost function. The cost function can be based on one or more independent criteria of the design, such wiring or routing costs, timing costs, and power consumption costs. The compilation phase can include clustering, placement, and routing of the design. One or more of the cost function criteria can include statistical attributes of the device. The compilation software can use statistical attributes of the device to predict device yields for a design. The compilation software can also predict device yields of a design using devices of different speed bin classifications.

US Patent:

20170017746, Jan 19, 2017

Filed:

Jul 13, 2015

Appl. No.:

14/798250

Inventors:

- Mountain View CA, US
Xiang Qui - Mountain View CA, US
Balkrishna R. Rashingkar - San Jose CA, US
Yan Lin - Pleasanton CA, US

Assignee:

SYNOPSYS, INC. - Mountain View CA

International Classification:

G06F 17/50

Abstract:

A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.

US Patent:

20140181773, Jun 26, 2014

Filed:

Dec 26, 2013

Appl. No.:

14/141207

Inventors:

- Mountain View CA, US
Yan Lin - Pleasanton CA, US
Aiguo Lu - San Jose CA, US
Balkrishna R. Rashingkar - San Jose CA, US
Russell B. Segal - Sunnyvale CA, US
Peiqing Zou - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716120

Abstract:

Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.