Yangsung J Joo

US Patent:

6728151, Apr 27, 2004

Filed:

Aug 29, 2002

Appl. No.:

10/233997

Inventors:

Yangsung Joo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365205, 36518909, 365222, 365226

Abstract:

Circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors are described. The source terminal of a low V PMOS transistor is maintained at ground potential during DRAM standby mode. The source terminal of the low V PMOS transistor is raised to an intermediate supply voltage responsive to a transition from DRAM standby mode to either DRAM read mode, write mode, or refresh mode and prior to development of a differential voltage between the gate and drain terminals of the low V PMOS transistor. These circuits and methods advantageously limit current loss through the low V PMOS transistor when the differential voltage develops between the gate and drain terminals of that low V PMOS transistor and in the event of a word line and digital line short-circuit.

US Patent:

6795361, Sep 21, 2004

Filed:

May 6, 2002

Appl. No.:

10/140411

Inventors:

Yangsung Joo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365222, 365 63, 36518901, 365226

Abstract:

An isolation signal line in a memory device having a standby power mode is configured to be exclusively held as either a logic high or logic low during some portion of the standby power mode and as the other of the logic high and logic low during another portion of the standby power mode to prevent unnecessary switching every time the memory device operates in standby power mode. As a result, memory devices having an upper and lower array achieve true electrical isolation during standby power modes and, if a row-to-column short exists, standby power mode current leakage is cut in half as compared to non-isolated arrays. The switching current necessary to drive the isolation signal line to a bootstrapped logic high during such standby power mode times is likewise prevented. In other embodiments, methods, electronic systems, wafers and DRAM are taught.

US Patent:

7002863, Feb 21, 2006

Filed:

Feb 20, 2004

Appl. No.:

10/783976

Inventors:

Yangsung Joo - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

365205, 36518909, 365222, 365226

Abstract:

Circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors are described. The source terminal of a low VPMOS transistor is maintained at ground potential during DRAM standby mode. The source terminal of the low VPMOS transistor is raised to an intermediate supply voltage responsive to a transition from DRAM standby mode to either DRAM read mode, write mode, or refresh mode and prior to development of a differential voltage between the gate and drain terminals of the low VPMOS transistor. These circuits and methods advantageously limit current loss through the low VPMOS transistor when the differential voltage develops between the gate and drain terminals of that low VPMOS transistor and in the event of a word line and digital line short-circuit.

US Patent:

7038958, May 2, 2006

Filed:

Aug 26, 2004

Appl. No.:

10/926357

Inventors:

Yangsung Joo - Boise ID, US
David L. Pinney - Boise ID, US
Jason Brown - Allen TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

365203, 365205, 365190, 365194

Abstract:

A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the conventional equilibrate process so that the positive portion and the negative portion of the sense amplifier are equilibrated at different times. Bit line equilibration can be associated with either the equilibrate step associated with the positive portion of the sense amplifier or the equilibrate step associated with the negative portion of the sense amplifier.

US Patent:

7103126, Sep 5, 2006

Filed:

Jan 17, 2002

Appl. No.:

10/051483

Inventors:

Yangsung Joo - Boise ID, US
Greg A. Blodgett - Nampa ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H04L 7/00
H04L 7/02

US Classification:

375354, 375355, 375356

Abstract:

A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

US Patent:

7116588, Oct 3, 2006

Filed:

Sep 1, 2004

Appl. No.:

10/932480

Inventors:

Yangsung Joo - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00

US Classification:

36518909, 36518911, 361 24, 327 83, 327138, 327355, 327361, 327378

Abstract:

A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with the thermal voltage to produce a reference voltage, the reference voltage is substantially insensitive to temperature. The forward junction voltage and the thermal voltage are combined to produce the reference voltage in a manner that avoids generating any voltage having a magnitude that is greater than the magnitude of the sum of the forward voltage and the thermal voltage.

US Patent:

7139345, Nov 21, 2006

Filed:

Aug 31, 2005

Appl. No.:

11/218170

Inventors:

Yangsung Joo - Boise ID, US
Greg A. Blodgett - Nampa ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H04L 7/00
H04L 7/02

US Classification:

375354, 375355, 375356

Abstract:

A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

US Patent:

7224631, May 29, 2007

Filed:

Aug 31, 2004

Appl. No.:

10/930322

Inventors:

Yangsung Joo - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/00
G11C 8/10

US Classification:

365222, 711202, 365149, 36523006

Abstract:

In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This causes a remapping circuit to remap a first memory address bit to an unused memory address location. Using the new addressing scheme, an auto-refresh operation is performed on the memory array operating in the half-density mode without skipping refresh commands.