Yao T Yen from 21638 Rosario Ave, Cupertino, CA 95014, age 88, Phone: 4082551129

Us Patents

Spread-Spectrum Clock Buffer/Driver That Modulates Clock Period By Switching Loads
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US Patent:

6501307, Dec 31, 2002
Filed:

Nov 12, 2001
Appl. No.:

09/683041
Inventors:

Yao Tung Yen - Cupertino CA
Assignee:

Pericom Semiconductor Corp. - San Jose CA
International Classification:

H03B 1900
US Classification:

327113, 327114, 327175
Abstract:

A clock modulator spreads the frequency spectrum of an input clock to generate an output clock. A capacitor is connected to an intermediate clock node by a load-switching transistor. When the transistor is turned on, the capacitor increases the loading on the intermediate clock node, increasing delay. When the transistor is turned off, the delay is reduced. Output clock cycle periods are extended when delay is added, and reduced when the transistor turns off. A counter or sequencer is clocked by the input clock and drives the load-switching transistor. The transistor is turned on and off for alternate cycles when the counter is a toggle flip-flop, spreading the frequency over two frequencies every two clock cycles. Two capacitors of different sizes, connected to the intermediate clock node by two transistors, can be switched by a 2-bit sequencer, spreading the output clock over 7 frequencies every 7 clock cycles.

Near-Zero Propagation-Delay Active-Terminator Using Transmission Gate
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US Patent:

6686763, Feb 3, 2004
Filed:

May 16, 2002
Appl. No.:

10/063827
Inventors:

Yao Tung Yen - Cupertino CA
Assignee:

Pericam Semiconductor Corp. - San Jose CA
International Classification:

H03K 19003
US Classification:

326 30, 326 31, 326 26, 326 27
Abstract:

A transmission line is terminated by a buffer. The buffer isolates a load from the transmission line using a transmission gate. The transmission gate is turned off and does not conduct most of the time, but turns on when a transition is detected on the transmission line, allowing the transmission line to directly drive the load for a short time. Once the load is switched beyond a logic threshold voltage, the transmission gate is again turned off and a latch or latching transistors driven by the transmission line continue to drive the isolated load to power or ground voltages. Driver transistors are also enabled when the transmission gate is turned on, driving either the output (load) node or the input (transmission line) node with the new data. Feedback from the output node disables the transmission gate and driver transistors once the output has been driven past the logic threshold.

Trace-Impedance Matching At Junctions Of Multi-Load Signal Traces To Eliminate Termination
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US Patent:

6927992, Aug 9, 2005
Filed:

Dec 1, 2003
Appl. No.:

10/707249
Inventors:

Yao Tung Yen - Cupertino CA, US
Assignee:

Pericom Semiconductor Corp. - San Jose CA
International Classification:

G11C005/06
US Classification:

365 63, 36518527, 365 51
Abstract:

A module board has trace impedances that are matched at trace junctions. An input line that drives a signal to a junction has its impedance adjusted to match the equivalent impedance of branch traces output from the junction. Since input and output impedances match, reflections caused by the junction are minimized or eliminated. The input impedance can match by being within 20% of the equivalent impedance of the branch lines. The equivalent impedance of branches is the reciprocal of the sum of the individual branch lines' reciprocal impedance. Termination can be eliminated when such junctions are impedance-matched. Secondary junctions can also be impedance-matched, allowing for a variety of trace topologies. Such trace-impedance matching is especially useful for memory modules.

Ddr Memory Modules With Input Buffers Driving Split Traces With Trace-Impedance Matching At Trace Junctions
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US Patent:

6947304, Sep 20, 2005
Filed:

May 12, 2003
Appl. No.:

10/249845
Inventors:

Yao Tung Yen - Cupertino CA, US
Assignee:

Pericon Semiconductor Corp. - San Jose CA
International Classification:

G11C005/06
US Classification:

365 63, 365 51, 36518905
Abstract:

A memory module has improved signal propagation delays for signals externally driven such as from a motherboard. Reflections from junctions of wiring traces on the memory module are reduced or eliminated. An input buffer or register receives a signal from the motherboard and splits the signal to drive two outputs to two separate traces. Each trace is enlarged in width or thickness, such as by using a double-width wiring trace. At the fare end of each double-width trace, a junction is made to two minimum-width traces that connect to small stub traces to DRAM inputs. Reflections from the junction are eliminated or reduced by trace-impedance matching, since the input impedance of the double-width trace from the input buffer is about the same as the combined impedance of the two minimum-width traces. Trace-input matching and input buffering can improve signal integrity and overall propagation delay.

Differential Clock Signals Encoded With Data
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US Patent:

7020208, Mar 28, 2006
Filed:

May 3, 2002
Appl. No.:

10/063621
Inventors:

Yao Tung Yen - Cupertino CA, US
Assignee:

Pericom Semiconductor Corp. - San Jose CA
International Classification:

H04B 14/06
US Classification:

375244, 375242, 375354, 375357, 375376
Abstract:

The number of pins on an integrated circuit chip is reduced by encoding control signals into a differential clock. The differential clock has two clock lines with complementary signals that together represent a clock. Control signals inside a clock-transmitting chip are input to an encoder which determines which control signal is being asserted or de-asserted. The encoder drives a clock-control signal that either forces both differential clock lines low or stops the differential clock from pulsing. A clock-receiving chip detects the both-low or stopped differential clock and determines which control signal was asserted or de-asserted. A phase-locked loop (PLL) in the receiver keeps an internal clock running even when the differential clock is missing pulses. A sequence of M1 missing clock pulses, followed by N1 clock pulses, followed by M2 missing pulses encodes the control signal, where M1, N1, and M2 are whole numbers.

Memory Module With Dynamic Termination Using Bus Switches Timed By Memory Clock And Chip Select
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US Patent:

7068064, Jun 27, 2006
Filed:

Jul 14, 2004
Appl. No.:

10/710475
Inventors:

Yao Tung Yen - Cupertino CA, US
Assignee:

Pericom Semiconductor Corp. - San Jose CA
International Classification:

H03K 19/03
H03K 17/16
G11C 5/06
US Classification:

326 30, 326 28, 365 63, 365233
Abstract:

A low-power memory module has an active termination circuit at each end of critical signal traces. The dynamic termination circuit has a low-value resistor that is connected to a termination voltage by a transmission gate that is turned on by a switch signal. The switch signal is activated when the memory module is selected by a chip-select signal, and when a time window is open. The time window is generated from the clock to synchronous DRAMs on the memory module. The time window can be one-quarter of the clock period by ANDing the clock and a delayed clock that is delayed by one-quarter of a cycle. A static terminating resistor in parallel with the low-value resistor provides a much smaller terminating current that is not switched on and off. Traces can be impedance-matched at junctions to branches that each has a dynamic termination circuit at the far end.

Adapter Board For Stacking Ball-Grid-Array (Bga) Chips
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US Patent:

7126829, Oct 24, 2006
Filed:

Feb 9, 2004
Appl. No.:

10/708101
Inventors:

Yao Tung Yen - Cupertino CA, US
Assignee:

Pericom Semiconductor Corp. - San Jose CA
International Classification:

H05K 1/11
H01L 23/538
US Classification:

361803, 361767, 361768, 361774, 361783, 257686
Abstract:

Electronic devices packaged with arrayed solder balls, leads, or pads, such as Ball Grid Array (BGA) devices, are stacked together. Each stack has a bottom adapter card with metal contacts on a top surface in an array to match the array of solder balls of a lower BGA package, and final bonding pads on a bottom surface that are soldered to an underlying motherboard or printed-circuit board (PCB). An upper BGA package has its solder balls connected to a matching array of metal contacts on a top surface of an intermediate adapter card. Metal traces on the intermediate adapter card connect to lead frame pins that wrap around the edge of the intermediate adapter card and make contact with peripheral pads on the top surface of the bottom adapter card. Lead frame pins and peripheral pads can connect several intermediate adapter cards together with one bottom adapter card.

Interconnector For Integrated Circuit Package
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US Patent:

40848698, Apr 18, 1978
Filed:

Nov 10, 1976
Appl. No.:

5/740390
Inventors:

Yao T. Yen - Cupertino CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H05K 112
US Classification:

339 17CF
Abstract:

An interconnector for providing coupling between an integrated circuit pin connector, a socket connector which may be part of a printed circuit board, and a cable. Some pins of the pin connector connect directly with sockets of the socket connector, other pins and sockets are coupled to the cable. When used in an in-circuit emulator for a microcomputer, the interconnector permits the CPU or microprocessor to be physically located on the microcomputer's circuit board during testing of the microcomputer. Some of the signals which normally flow between the CPU or microprocessor and the remainder of the microcomputer are diverted to the cable. This permits sensing of signals intended for the CPU or microprocessor and the substitution of other signals in place of the sensed signals.