Yaron Kretchmer

US Patent:

7139991, Nov 21, 2006

Filed:

Apr 14, 2005

Appl. No.:

11/107585

Inventors:

Yaron Kretchmer - Fremont CA, US
Michael Porter - Milpitas CA, US
Thomas Obrien - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 9, 716 1, 716 12

Abstract:

A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.

US Patent:

7365413, Apr 29, 2008

Filed:

Sep 13, 2004

Appl. No.:

10/940511

Inventors:

Yaron Kretchmer - Fremont CA, US
Fredrik Haghverdian - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 29/06

US Classification:

257618, 257621, 257622, 257773, 257774, 257776, 257797, 257E2926, 257E21553, 257E21555, 257E21577

Abstract:

Electrical interconnects with a slotting pattern are provided in the present invention. In addition, the masks for making such interconnects and semiconductor devices incorporating such interconnects are also provided in the present invention. The slotting pattern may be designed to minimize dishing effects of the interconnects as a result of planarization. Further, the slotting pattern may be designed to minimize resistance in the interconnects. For instance, the slotting pattern may include slots that are staggered, evenly aligned, or a combination of both staggered and evenly aligned. In addition, the slots may be spaced apart such that electrical paths are shorter across the interconnects. By incorporating such interconnects in semiconductor devices, better performing semiconductor devices can be realized.

US Patent:

7861190, Dec 28, 2010

Filed:

Mar 17, 2005

Appl. No.:

10/907049

Inventors:

Yaron Kretchmer - Fremont CA, US
Paul Leventis - Toronto, CA
Vaughn Betz - Toronto, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 16

Abstract:

An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

US Patent:

8099692, Jan 17, 2012

Filed:

Nov 24, 2010

Appl. No.:

12/953764

Inventors:

Yaron Kretchmer - Fremont CA, US
Paul Leventis - Toronto, CA
Vaughn Betz - Toronto, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716100

Abstract:

An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

US Patent:

6931606, Aug 16, 2005

Filed:

Oct 15, 2001

Appl. No.:

09/978141

Inventors:

Yaron Kretchmer - Fremont CA, US
Michael Porter - Milpitas CA, US
Thomas OBrien - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F017/50
G06F009/45

US Classification:

716 1, 716 12, 716 9

Abstract:

A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.