Yen M Lee

US Patent:

7310226, Dec 18, 2007

Filed:

Nov 22, 2005

Appl. No.:

11/283974

Inventors:

Richard Chen - San Jose CA, US
Yen Lun Lee - Fremont CA, US

Assignee:

Super Micro Computer, Inc. - San Jose CA

International Classification:

H05K 7/20

US Classification:

361695, 361692, 361697, 361719, 165 803, 16510433, 165121, 165185, 257712, 257722, 174 163

Abstract:

A modularized redundant heat sink for dissipating heat generated from chips includes an independent rectangular fin whose sides are provided with at least more than two elastic pins, and which is provided with a bottom surface for conducting temperature; a circuit board on which are welded with at least more than two chips having upper surfaces. A bottom surface of the fin is attached to the upper surfaces of at least more than two chips through a heat conducting glue, so as to provide a temperature conducting and heat dissipating to at least more than two chips by one fin.

US Patent:

7363353, Apr 22, 2008

Filed:

Jul 8, 2002

Appl. No.:

10/191746

Inventors:

Elango Ganesan - Palo Alto CA, US
Ramesh Panwar - Pleasanton CA, US
Yen Lee - San Jose CA, US
Chau Anh Ngoc Nguyen - San Jose CA, US
John Phillips - Santa Clara CA, US
Yuhong Andy Zhou - Alameda CA, US
Gregory G Spurrier - Sunnyvale CA, US
Michael Freed - Pleasanton CA, US
Mark Bryers - Granite Bay CA, US
Nazar Zaidi - San Jose CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 15/16

US Classification:

709218, 709203, 709201, 370235

Abstract:

An architecture for controlling a multiprocessing system to provide at least one network service to subscriber data packets transmitted in the system using a plurality of compute elements, comprising a management compute element including service set-up information for at least one service and at least one processing compute element applying said at least one network service to said data packets and communicating service set-up information with the management compute element in order to perform service specific operations on data packets. In a further embodiment, a method of controlling a processing system including a plurality of processors is disclosed. The method comprises the steps of operating at least one of said processors as a control authority providing service provisioning information for a subscriber; and operating a set of processors as a service specific compute element responsive to the control authority, receiving provisioning information from the subscriber and performing service specific instructions on data packets to provide IP content services.

US Patent:

20130155861, Jun 20, 2013

Filed:

Feb 4, 2013

Appl. No.:

13/758878

Inventors:

JUNIPER NETWORKS, INC. - Sunnyvale CA, US
Elango Ganesan - Palo Alto CA, US
Frederick Gruner - Palo Alto CA, US
David Hass - Santa Clara CA, US
Robert Hathaway - Sunnyvale CA, US
Ramesh Panwar - Pleasanton CA, US
Ricardo Ramirez - Sunnyvale CA, US
Abbas Rashid - Fremont CA, US
Mark Vilas - San Jose CA, US
Nazar Zaidi - San Jose CA, US
Yen Lee - San Jose CA, US
Chau Anh Ngoc Nguyen - San Jose CA, US
John Phillips - Santa Clara CA, US
Yuhong Zhou - Alameda CA, US
Gregory G. Spurrier - Sunnyvale CA, US
Michael Freed - Fremont CA, US

Assignee:

JUNIPER NETWORKS, INC. - Sunnyvale CA

International Classification:

H04L 12/56

US Classification:

370235

Abstract:

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

US Patent:

58840877, Mar 16, 1999

Filed:

Apr 3, 1997

Appl. No.:

8/826613

Inventors:

Dave White - San Jose CA
Yen Wei Lee - San Jose CA
Rod Ang - San Jose CA
Ray Barbieri - Campbell CA
James Chen - Taipei, TW
Suh Chiueh Lee - Palo Alto CA

Assignee:

Smith Corona/Acer

International Classification:

G06F 1556
G06F 1516
G06B 1502

US Classification:

39575002

Abstract:

A power management system for a personal computer comprises a power management processor, a switchable power supply and a keep alive power supply. The processor is powered by the keep alive power supply that continuously provides power. The computer is powered by a power supply that is switchable in response to a control signal. The processor preferably controls the switchable power supply. The processor is coupled to receive external device interrupts from a plurality of external devices that instruct the processor when to turn the switchable power supply on and off. The processor is also coupled to the computer through an interface. The power management system also includes a method for turning the computer on and off. A preferred method uses the processor to control the power provided to the computer. The preferred method also uses the processor to dictate whether the computer will to perform a long boot that brings the computer to an operational state, identifies the computer's configuration, and tests memory, or a short boot that brings the computer to an operational state in a much shorter time.

US Patent:

59037652, May 11, 1999

Filed:

Apr 3, 1997

Appl. No.:

8/825663

Inventors:

Dave White - San Jose CA
Yen Wei Lee - San Jose CA
Rod Ang - San Jose CA
Ray Barbieri - Campbell CA
James Chen - Taipei, TW
Suh Chiueh Lee - Palo Alto CA

Assignee:

Smith Corona/Acer

International Classification:

G06F1/26;1/32

US Classification:

39575002

Abstract:

A power management system for a personal computer comprises a power management processor, a switchable power supply and a keep alive power supply. The processor is powered by the keep alive power supply that continuously provides power. The computer is powered by a power supply that is switchable in response to a control signal. The processor preferably controls the switchable power supply. The processor is coupled to receive external device interrupts from a plurality of external devices that instruct the processor when to turn the switchable power supply on and off. The processor is also coupled to the computer through an interface. The power management system also includes a method for turning the computer on and off. A preferred method uses the processor to control the power provided to the computer. The preferred method also uses the processor to dictate whether the computer will perform a long boot that brings the computer to an operational state, identifies the computer's configuration, and tests memory, or a short boot that brings the computer to an operational state in a much shorter time.

US Patent:

57873020, Jul 28, 1998

Filed:

May 15, 1996

Appl. No.:

8/649731

Inventors:

Hari Hampapuram - Sunnyvale CA
Yen C. Lee - San Jose CA
Eino Jacobs - Palo Alto CA
Michael Ang - Santa Clara CA

Assignee:

Philips Electronic North America Corporation - New York NY

International Classification:

G06F 700

US Classification:

39580024

Abstract:

Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

US Patent:

58623981, Jan 19, 1999

Filed:

May 15, 1996

Appl. No.:

8/649732

Inventors:

Hari Hampapuram - Sunnyvale CA
Yen C. Lee - Sunnyvale CA
Michael Ang - Santa Clara CA
Eino Jacobs - Palo Alto CA

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

G06F 1300

US Classification:

39580024

Abstract:

The software which produces a shuffled bit stream which bit stream allows for a simplified cache layout. This object is met using computer software which includes code for receiving a compiled and linked object module produced by a compiler and/or linker and code for swizzling the compiled and linked software to produce a second object module. The second object module is suitable for being deswizzled upon reading from a cache memory using a cache structure whose output bus wires are not crossed.

US Patent:

59637447, Oct 5, 1999

Filed:

Apr 30, 1997

Appl. No.:

8/836852

Inventors:

Gerrit Ary Slavenburg - Los Altos CA
Pieter van der Meulen - Sunnyvale CA
Yong Cho - Princeton NJ
Vijay K. Mehra - Fremont CA
Yen C. Lee - San Jose CA

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

G06F 1516
G06F 1580
G06F 1716

US Classification:

39580009

Abstract:

Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i. e. , low cost and chip count, and advantages of a general-purpose processor reprogramability. These custom operations work in a computer system which supplies input data having operand data, performs operations on the operand data, and supplies result data to a destination register. Operations performed may include audio and video processing including clipping or saturation operations. The present invention also performs parallel operations on select operand data from input registers and stores results in the destination register.