Yen Pang Lin

US Patent:

20110161553, Jun 30, 2011

Filed:

Dec 30, 2009

Appl. No.:

12/649992

Inventors:

Nirmal Saxena - Los Altos Hill CA, US
Howard Tsai - Cupertino CA, US
Dmitry Vyshetsky - Cupertino CA, US
Yen Lin - Saratoga CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 12/06
G06F 12/00

US Classification:

711103, 711206, 711118, 711E12078, 711E12001

Abstract:

The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits.