Yin Y Ma

US Patent:

7408752, Aug 5, 2008

Filed:

May 30, 2007

Appl. No.:

11/755631

Inventors:

Yin Tat Ma - Diamond Bar CA, US
Guann Pyng Li - Irvine CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H02H 9/00
H02H 3/20
H02H 9/04
H02H 3/22
H02H 7/00

US Classification:

361 56, 361 911, 361111, 361 18

Abstract:

A low loading capacitance on-chip electrostatic discharge (ESD) protection circuit for compound semiconductor power amplifiers is disclosed, which does not degrade the circuit RF performance. Its principle of operation and simulation results regarding capacitance loading, leakage current, degradation to RF performance are disclosed. The design, loading effect over frequency, robustness over process and temperature variation and application to an RF power amplifier is presented in detail. The ESD circuit couples an input to ground during ESD surges through a diode string coupled to the input, and a transistor switch or Darlington pair having its gate coupled to and triggered by the diode string. The Darlington pair couples the input to ground when triggered through a low impedance path in parallel to the diode string. A reverse diode also couples ground to the input on reverse surges.

US Patent:

7423490, Sep 9, 2008

Filed:

Mar 31, 2006

Appl. No.:

11/395827

Inventors:

Yin Tat Ma - Diamond Bar CA, US
Jonathan Bruce Hacker - Thousand Oaks CA, US

Assignee:

Rockwell Scientific Licensing, LLC - Thousand Oaks CA

International Classification:

H03F 3/191

US Classification:

330297, 330306, 333181

Abstract:

An n-stage RF choke comprises a series connection of two or more inductors connected in series between a source and a load. The inductor closest to the source has the largest inductance and the inductance closest to the load has the smallest inductance. The inductances of any inductors between the inductor closest to the supply and the inductor closest to the load decrease as a function of distance from the supply. The junctions between the inductors in the series connection are shunted to ground by capacitors connected in series with resistors that provide a matched termination for increasing bandwidth by lowering circuit Q factors and eliminating resonant frequencies. The capacitor closest to the supply has the largest capacitance and the capacitor closest to the load has the smallest capacitance. Any intermediate capacitors decrease in capacitance as a function of distance from the supply. Such an arrangement provides a high impedance that isolates the load from the supply at a wide range of frequencies.

US Patent:

20050122644, Jun 9, 2005

Filed:

Jan 16, 2003

Appl. No.:

10/501651

Inventors:

Yin Ma - Diamond Bar CA, US

International Classification:

H02H009/00

US Classification:

361056000

Abstract:

A low loading capacitance on-chip electrostatic discharge (ESD) protection circuit for compound semiconductor power amplifiers is disclosed, which does not degrade the circuit RF performance. Its principle of operation and simulation results regarding capacitance loading, leakage current, degradation to RF performance are disclosed. The design, loading effect over frequency, robustness over process and temperature variation and application to an RF Power amplifier is presented in detail. The ESD circuit couples an input to ground during ESD surges through a diode string coupled to the input, and a transistor switch or Darlington pair having its gate coupled to and triggered by the diode string. The Darlington pair couples the input to ground when triggered through a low impedance path in parallel to the diode string. A reverse diode also couples ground to the input on reverse surges.