Ngok Ying Chu

US Patent:

7194008, Mar 20, 2007

Filed:

Sep 11, 2002

Appl. No.:

10/238805

Inventors:

Ngok Ying Chu - San Jose CA, US
John M. Chiang - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04J 3/06

US Classification:

370465, 370503

Abstract:

A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.

US Patent:

7970962, Jun 28, 2011

Filed:

Oct 15, 2002

Appl. No.:

10/269989

Inventors:

Ngok Ying Chu - San Jose CA, US
John M. Chiang - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 13/00
G06F 13/12
G06F 15/173
G06F 15/16
G01R 31/08
H04B 7/216
H04L 12/28
H04J 3/16
G10H 7/04
G10H 1/00

US Classification:

710 34, 710 33, 710 35, 710 72, 370234, 370335, 370389, 3703951, 370400, 370471, 709226, 709250, 84605, 84606

Abstract:

A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.

US Patent:

20030182613, Sep 25, 2003

Filed:

Sep 5, 2002

Appl. No.:

10/234165

Inventors:

Ngok Chu - San Jose CA, US

Assignee:

Broadcom Corporation

International Classification:

H03M013/00

US Classification:

714/758000

Abstract:

A logic circuit includes an interface and an error detection unit. The interface is configured to receive and transmit a data stream, wherein the data stream includes at least one of a variable length burst and a fixed length burst. The error detection unit is configured to detect an error detection code when a misalignment occurs within the data stream by calculating recursive terms.

US Patent:

20070133615, Jun 14, 2007

Filed:

Feb 6, 2007

Appl. No.:

11/702578

Inventors:

Ngok Chu - San Jose CA, US
John Chiang - San Jose CA, US

International Classification:

H04J 3/06

US Classification:

370503000

Abstract:

A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.

US Patent:

20130275827, Oct 17, 2013

Filed:

Apr 12, 2012

Appl. No.:

13/445834

Inventors:

Chung-Li Wang - San Jose CA, US
Lei Chen - Santa Clara CA, US
Shaohua Yang - San Jose CA, US
Zongwang Li - Santa Clara CA, US
Herjen Wang - Sunnyvale CA, US
Ngok Ying Chu - Los Altos CA, US
Johnson Yen - Fremont CA, US

International Classification:

H03M 13/05
G06F 11/10

US Classification:

714752, 714E11032

Abstract:

Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages.

US Patent:

20130305114, Nov 14, 2013

Filed:

May 10, 2012

Appl. No.:

13/468968

Inventors:

Sancar K. Olcay - Sunnyvale CA, US
Lei Chen - Santa Clara CA, US
Madhusudan Kalluri - Sunnyvale CA, US
Johnson Yen - Fremont CA, US
Ngok Ying Chu - Los Altos CA, US

International Classification:

H03M 13/05
G06F 11/10
H03M 13/29

US Classification:

714755, 714752, 714E11032

Abstract:

Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.

US Patent:

20140068164, Mar 6, 2014

Filed:

Sep 4, 2012

Appl. No.:

13/603076

Inventors:

Herjen Wang - Sunnyvale CA, US
Lei Chen - Sunnyvale CA, US
Ngok Ning Chu - Los Altos CA, US
Johnson Yen - Fremont CA, US

Assignee:

LSI CORPORATION - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711104, 711154, 711E12001

Abstract:

A memory content access interface may include, but is not limited to: a read-path memory partition; a write-path memory partition; and a memory access controller configured to regulate access to at least one of the read-path memory partition and the write-path memory partition by an external controller.

US Patent:

20140068389, Mar 6, 2014

Filed:

Sep 4, 2012

Appl. No.:

13/603104

Inventors:

Ngok Ning Chu - Los Altos CA, US
Lei Chen - Sunnyvale CA, US
Herjen Wang - Sunnyvale CA, US
Johnson Yen - Fremont CA, US

Assignee:

LSI CORPORATION - Milpitas CA

International Classification:

H03M 13/05
H03M 13/27

US Classification:

714780, 714E11032

Abstract:

Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.