Yiran Chen from Chicago, IL, age 32

Intern

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Location:

Minneapolis, MN

Industry:

Real Estate

Work:

Apex Comercial Real Estate
Intern

Education:

University of St. Thomas 2014 - 2016
Masters, Real Estate Beijing Normal University, Zhuhai 2010 - 2014
Bachelors, Real Estate, Management

Local Teacher

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Location:

San Diego, CA

Industry:

Marketing And Advertising

Work:

Dreamaker Drama Academy
Local Teacher
Broadstone Business Solutions
Brand Ambassador
Tellon Trading Nov 2017 - Mar 2018
Marketing Coordinator
Verif-Y Inc. Jul 2017 - Oct 2017
Marketing Analyst
Xin Lv Meng Farming Technology Jun 2015 - Sep 2015
Marketing Manager

Education:

Drexel University 2016 - 2018
Masters, Marketing Drexel University 2012 - 2016
Bachelors, Bachelor of Arts, Bachelor of Business Administration, Marketing

Skills:

Management
Powerpoint
Marketing
Microsoft Powerpoint
Event Planning
Public Relations
Leadership
Marketing Communications
Microsoft Word
Microsoft Excel
Adobe Premiere Pro
Adobe Photoshop
Itunes Connect
Blockchain
Teamwork
Direct Marketing
Blogging
English
Photography
Customer Relations Management
Spss
Social Media Marketing
Event Management
Website Design
Business Analysis
A/B Testing

Languages:

English
Mandarin
Japanese
French

Summer Law Intern

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Location:

1010 2Nd Ave, San Diego, CA 92101

Industry:

Law Practice

Work:

Medpro Group
Summer Law Intern
Heavner, Beyers & Mihlar, Llc May 2015 - Aug 2015
Summer Law Clerk
Gaston and Gaston Jul 2013 - Jul 2015
Client Relations Liaison
Walter & Caietti A.p.c Aug 2012 - Jul 2013
Law Clerk
Independent Voter Project Jul 2012 - Aug 2012
Regional Political Director

Education:

University of Illinois College of Law 2014 - 2017
Uc San Diego 2010 - 2013
Bachelors, Bachelor of Arts, Political Science

Skills:

Event Planning
Microsoft Office
Microsoft Word
Legal Writing
Powerpoint
Research
Microsoft Excel
Public Speaking
Legal Research
Westlaw

Languages:

Mandarin

Certifications:

Westlawnext Certified
Lexisnexis Certified

International Student Services

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Location:

Minneapolis, MN

Industry:

Real Estate

Work:

University of St. Thomas
International Student Services
Apex Commercial Properties, Llc Apr 2015 - Nov 2015
Project Coordinator

Configuration Analyst

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Location:

Richardson, TX

Work:

Voya Financial
Configuration Analyst

Education:

University of St. Thomas

Yiran Chen

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Location:

429 Belle Gate Pl, Cary, NC

Industry:

Computer Hardware

Work:

Duke University Jan 2017 - Jul 2019
Professor
University of Pittsburgh Jan 2017 - Jul 2019
Associate Professor, Bicentennial Alumni Faculty Fellow
University of Pittsburgh Aug 2010 - Aug 2014
Assistant Professor
Seagate Technology Apr 2007 - Aug 2010
Staff Engineer
Synopsys Jul 2005 - Apr 2007
Senior R and D Engineer I

Education:

Purdue University 2001 - 2005
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy Tsinghua University 1998 - 2001
Masters, Engineering Tsinghua University 1994 - 1998
Bachelors, Bachelor of Science, Engineering, Electronics Engineering, Electronics Tsinghua University
Master of Science, Masters

Skills:

Vlsi
Semiconductors
Eda
Circuit Design
Computer Architecture
Algorithms
Simulations
Sensors
Low Power Design
Matlab
Fpga
Embedded Systems
Static Timing Analysis
C
R&D
High Performance Computing
Ic
Entrepreneurship
Very Large Scale Integration
Signal Processing
Nanotechnology
Higher Education
Verilog
Research and Development
Asic
Analog Circuit Design
Higher Education
Vlsi and Eda
Integrated Circuit Design
Vhdl
Soc
Digital Signal Processors
Silicon
High Performance Computing
Microprocessors

Staff Engineer

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Location:

Eden Prairie, MN

Industry:

Computer Hardware

Work:

Seagate Technology
Staff Engineer

Yiran Chen

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Work:

People's Bank of China

Education:

University of International Business and Economics

Us Patents

Oscillating Current Assisted Spin Torque Magnetic Memory
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US Patent:

7800938, Sep 21, 2010
Filed:

Oct 15, 2008
Appl. No.:

12/251603
Inventors:

Kirill Rivkin - Edina MN, US
Yiran Chen - Eden Prairie MN, US
Xiaobin Wang - Chanhassen MN, US
Haiwen Xi - Prior Lake MN, US
Assignee:

Seagate Technology, LLC - Scotts Valley CA
International Classification:

G11C 11/00
US Classification:

365158, 365171, 365173
Abstract:

A memory unit having a spin torque memory cell with a ferromagnetic free layer, a ferromagnetic pinned layer and a spacer layer therebetween, with the free layer having a switchable magnetization orientation with a switching threshold. A DC current source is electrically connected to the spin torque memory cell to cause spin transfer torque in the free layer. An AC current source is electrically connected to the spin torque memory cell to produce an oscillatory polarized current capable of spin transfer torque via resonant coupling with the free layer.

Diode Assisted Switching Spin-Transfer Torque Memory Unit
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US Patent:

7804709, Sep 28, 2010
Filed:

Jul 18, 2008
Appl. No.:

12/175724
Inventors:

Xuguang Wang - Eden Prairie MN, US
Yiran Chen - Eden Prairie MN, US
Dimitar V. Dimitrov - Edina MN, US
Hongyue Liu - Maple Grove MN, US
Xiaobin Wang - Chanhassen MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

G11C 11/14
US Classification:

365171, 365173, 365158, 365175
Abstract:

A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.

Spin-Transfer Torque Memory Self-Reference Read And Write Assist Methods
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US Patent:

7813168, Oct 12, 2010
Filed:

Feb 17, 2009
Appl. No.:

12/372190
Inventors:

Wenzhong Zhu - Apple Valley MN, US
Yiran Chen - Eden Prairie MN, US
Dimitar V. Dimitrov - Edina MN, US
Xiaobin Wang - Chanhassen MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

G11C 11/14
US Classification:

365171, 365157, 365158, 365131, 365 97, 36518904
Abstract:

A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and the bit line read voltage is stored and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a magnetic field to the MTJ and then writing the desired resistance state are also disclosed.

Variable Write And Read Methods For Resistive Random Access Memory
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US Patent:

7826255, Nov 2, 2010
Filed:

Sep 15, 2008
Appl. No.:

12/210526
Inventors:

Haiwen Xi - Prior Lake MN, US
Hongyue Liu - Maple Grove MN, US
Xiaobin Wang - Chanhassen MN, US
Yong Lu - Rosemount MN, US
Yiran Chen - Eden Prairie MN, US
Yuankai Zheng - Bloomington MN, US
Dimitar V. Dimitrov - Edina MN, US
Dexin Wang - Eden Prairie MN, US
Hai Li - Eden Prairie MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

G11C 11/00
G11C 11/14
US Classification:

365158, 365148, 365163, 365171
Abstract:

Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.

Spin-Transfer Torque Memory Self-Reference Read And Write Assist Methods
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US Patent:

7826260, Nov 2, 2010
Filed:

Feb 17, 2009
Appl. No.:

12/372180
Inventors:

Wenzhong Zhu - Apple Valley MN, US
Yiran Chen - Eden Prairie MN, US
Xiaobin Wang - Chanhassen MN, US
Zheng Gao - Savage MN, US
Haiwen Xi - Prior Lake MN, US
Dimitar V. Dimitrov - Edina MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

G11C 11/14
US Classification:

365171, 365173, 365213, 365131, 365 48, 365 50
Abstract:

A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell, the magnetic field rotates the magnetization orientation of the free magnetic layer without switching a resistance state of the magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and the bit line read voltage is stored and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a destabilizing magnetic field to the MTJ and then writing the desired resistance state are also disclosed.

Resistive Sense Memory Array With Partial Block Update Capability
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US Patent:

7830700, Nov 9, 2010
Filed:

Nov 12, 2008
Appl. No.:

12/269564
Inventors:

Yiran Chen - Eden Prairie MN, US
Daniel S. Reed - Maple Plain MN, US
Yong Lu - Edina MN, US
Harry Hongyue Liu - Maple Grove MN, US
Hai Li - Eden Prairie MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

G11C 11/00
US Classification:

365148, 365100, 36523003, 365235, 36518904, 36523001
Abstract:

Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

Enhancing Read And Write Sense Margins In A Resistive Sense Element
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US Patent:

7852660, Dec 14, 2010
Filed:

Apr 17, 2009
Appl. No.:

12/425856
Inventors:

Wenzhong Zhu - Apple Valley MN, US
Hai Li - Eden Prairie MN, US
Yiran Chen - Eden Prairie MN, US
Xiaobin Wang - Chanhassen MN, US
Henry Huang - Apple Valley MN, US
Haiwen Xi - Prior Lake MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

G11C 11/00
G11C 11/14
G11C 17/00
US Classification:

365148, 365100, 365158, 365171
Abstract:

An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction and an easy programming direction. A write current is applied in either the hard programming direction or the easy programming direction to set the RSE to a selected programmed state. A read circuit subsequently passes a read sense current through the cell in the hard programming direction to sense the selected programmed state of the cell.

Memory Cell With Proportional Current Self-Reference Sensing
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US Patent:

7852665, Dec 14, 2010
Filed:

Mar 18, 2009
Appl. No.:

12/406356
Inventors:

Yiran Chen - Eden Prairie MN, US
Hai Li - Eden Prairie MN, US
Wenzhong Zhu - Apple Valley MN, US
Xiaobin Wang - Chanhassen MN, US
Ran Wang - Bloomington MN, US
Harry Hongyue Liu - Maple Grove MN, US
Assignee:

Seagate Technology LLC - Scotts Valley CA
International Classification:

G11C 11/00
US Classification:

365158, 365171, 365163, 365148, 365207
Abstract:

Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.