- Cupertino CA, US Chih-Ming Chung - Cupertino CA, US Jun Zhai - Cupertino CA, US Yifan Kao - Taoyuan, TW Young Doo Jeon - San Jose CA, US Taegui Kim - San Jose CA, US
International Classification:
H01L 23/00
Abstract:
Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.
Apple Inc. - Cupertino, CA since Jul 2011
Engineer
Broadcom Nov 2010 - Jul 2011
Sr. Staff Package Engineer
NVIDIA Oct 2007 - Nov 2010
Packaging Interconnect Engineer
Samsung Electro-mechanics Aug 2004 - Sep 2007
Senior R&D Manager
Education:
Korea Advanced Institute of Science and Technology 1994 - 2004
B.S., M.S., Ph.D., Material Science & Engineering