Yu Chen

Address:

4631 66 St, Woodside, NY 11377

VIN:

1G6DW677370185003

Make:

CADILLAC

Model:

STS

Year:

2007

US Patent:

7030412, Apr 18, 2006

Filed:

May 5, 2000

Appl. No.:

09/565413

Inventors:

Paul S. Drzaic - Lexington MA, US
Karl R. Amundson - Cambridge MA, US
Gregg M. Duthaler - Brookline MA, US
Peter T. Kazlas - Sudbury MA, US
Yu Chen - Cambridge MA, US

Assignee:

E Ink Corporation - Cambridge MA

International Classification:

H01L 29/04

US Classification:

257 59, 257 72

Abstract:

A thin-film transistor array comprises at least first and second transistors. Each transistor comprises a source electrode, a drain electrode a semiconductor electrode, a gate electrode, and a semiconductor layer. The semiconductor layer is continuous between the first and second transistors. The semiconductor layer is preferably unpatterned. In various display applications, the geometry of the transistors is selected to provide acceptable leakage currents. In a preferred embodiment, the transistor array is employed in an encapsulated electrophoretic display.

US Patent:

7091396, Aug 15, 2006

Filed:

Oct 17, 2001

Appl. No.:

09/982120

Inventors:

Sanford M. Simon - New York NY, US
Yu Chen - New York NY, US

Assignee:

The Rockefeller University - New York NY

International Classification:

A01K 67/027
A01K 67/033
C12N 15/63
C12N 5/06
C12N 5/10

US Classification:

800 18, 800 13, 435326, 435325, 435455, 4353201

Abstract:

Genetically-modified mammals and immune cells are provided which are capable of producing or secreting detectably-labeled immunoglobulin molecules as a result of genetic modifications of at least one immunoglobulin gene in the genome thereof, such that a fusion polynucleotide encoding a detectable protein or peptide and an immunoglobulin component molecule is present.

US Patent:

7116318, Oct 3, 2006

Filed:

Apr 24, 2003

Appl. No.:

10/249618

Inventors:

Karl R. Amundson - Cambridge MA, US
Yu Chen - Allston MA, US
Kevin L. Denis - Beverly Farms MA, US
Paul S. Drzaic - Morgan Hill CA, US
Peter T. Kazlas - Sudbury MA, US
Andrew P. Ritenour - Medford MA, US

Assignee:

E Ink Corporation - Cambridge MA

International Classification:

G09G 5/00

US Classification:

345204, 345205, 345210, 345214

Abstract:

A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.

US Patent:

7190008, Mar 13, 2007

Filed:

Oct 27, 2004

Appl. No.:

10/904160

Inventors:

Karl R. Amundson - Cambridge MA, US
Andrew P. Ritenour - Medford MA, US
Gregg M. Duthaler - Needham MA, US
Paul S. Drzaic - Morgan Hill CA, US
Yu Chen - Milpitas CA, US
Peter T. Kazlas - Sudbury MA, US

Assignee:

E Ink Corporation - Cambridge MA

International Classification:

H01L 27/148
H01L 29/768

US Classification:

257226, 257222, 359 51

Abstract:

An electro-optic display comprises a substrate (), non-linear devices () disposed substantially in one plane on the substrate (), pixel electrodes () connected to the non-linear devices (), an electro-optic medium () and a common electrode () on the opposed side of the electro-optic medium () from the pixel electrodes (). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices ().

US Patent:

7442587, Oct 28, 2008

Filed:

Jun 15, 2006

Appl. No.:

11/424258

Inventors:

Karl R. Amundson - Cambridge MA, US
Guy M. Danner - Somerville MA, US
Gregg M. Duthaler - Needham MA, US
Peter T. Kazlas - Sudbury MA, US
Yu Chen - Milpitas CA, US
Kevin L. Denis - Bowie MD, US
Nathan R. Kane - Arlington MA, US
Andrew P. Ritenour - Arlington MA, US

Assignee:

E Ink Corporation - Cambridge MA

International Classification:

H01L 21/00

US Classification:

438149, 257 59, 257E21094, 257E21104

Abstract:

A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors. The invention also provides a process for forming a diode on a substrate by depositing on the substrate a first conductive layer, and a second patterned conductive layer and a patterned dielectric layer over parts of the first conductive layer, and etching the first conductive layer using the second conductive layer and dielectric layer as an etch mask. Finally, the invention provides a process for driving an impulse-sensitive electro-optic display.

US Patent:

7605799, Oct 20, 2009

Filed:

Jul 31, 2006

Appl. No.:

11/461255

Inventors:

Karl R. Amundson - Cambridge MA, US
Yu Chen - Milpitas CA, US
Kevin L. Denis - Bowie MD, US
Paul S. Drzaic - Morgan Hill CA, US
Peter T. Kazlas - Sudbury MA, US
Andrew P. Ritenour - Arlington MA, US

Assignee:

E Ink Corporation - Cambridge MA

International Classification:

G09G 3/34

US Classification:

345107

Abstract:

A thin-film transistor includes a gate electrode having first and second gate electrode edges on opposed sides, and a drain electrode having a first edge that overlaps the first gate electrode edge, and a second edge that overlaps the second gate electrode edge. A diode array is fabricated by successive deposition of a conductive layer, a doped semiconductor layer and an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts using a source line and a balance line.

US Patent:

7785988, Aug 31, 2010

Filed:

Oct 1, 2008

Appl. No.:

12/243411

Inventors:

Karl R. Amundson - Cambridge MA, US
Guy M. Danner - Somerville MA, US
Gregg M. Duthaler - Needham MA, US
Peter T. Kazlas - Sudbury MA, US
Yu Chen - Milpitas CA, US
Kevin L. Denis - Bowie MD, US
Nathan R. Kane - Arlington MA, US
Andrew P. Ritenour - Arlington MA, US

Assignee:

E Ink Corporation - Cambridge MA

International Classification:

H01L 21/30

US Classification:

438458, 257E216

Abstract:

A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors. The invention also provides a process for forming a diode on a substrate by depositing on the substrate a first conductive layer, and a second patterned conductive layer and a patterned dielectric layer over parts of the first conductive layer, and etching the first conductive layer using the second conductive layer and dielectric layer as an etch mask. Finally, the invention provides a process for driving an impulse-sensitive electro-optic display.

US Patent:

7893435, Feb 22, 2011

Filed:

Nov 25, 2003

Appl. No.:

10/707184

Inventors:

Peter T. Kazlas - Sudbury MA, US
Joanna F. Au - Brighton MA, US
Yu Chen - Milpitas CA, US
Nathan R. Kane - Arlington MA, US
David John Cole - Medway MA, US

Assignee:

E Ink Corporation - Cambridge MA

International Classification:

H01L 29/04

US Classification:

257 59, 257E51005, 257E29151, 359242, 359243, 359245, 438149

Abstract:

A backplane for use in an electro-optic display comprises a patterned metal foil having a plurality of apertures extending therethrough, coated on at least side with an insulating polymeric material and having a plurality of thin film electronic devices provided on the insulating polymeric material.