Yu Chun Cheng

US Patent:

6949469, Sep 27, 2005

Filed:

Dec 16, 2003

Appl. No.:

10/738360

Inventors:

Yu Cheng - Fremont CA, US
Helen Zhu - Fremont CA, US
Hanzhong Xiao - Pleasanton CA, US
Peter K. Loewenhardt - Pleasanton CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L021/302
H01L021/461

US Classification:

438725, 438710

Abstract:

In a plasma processing system, a method of minimizing the differences in an etch rate of a photo resist material in different regions of a substrate is disclosed. The method includes introducing the substrate having in sequential order thereon, an underlying layer and the photo-resist layer. The method also includes flowing the etchant gas mixture into a plasma reactor of the plasma processing system, the etchant gas mixture comprising a flow of a fluorine containing gas between about 0. 1% and about 10% of the etchant gas mixture. The method further includes striking a plasma from the gas mixture; etching the photo-resist layer with the plasma; and, removing the substrate from the plasma reactor.

US Patent:

7412570, Aug 12, 2008

Filed:

Feb 9, 2006

Appl. No.:

11/351058

Inventors:

Laurent R. Moll - San Jose CA, US
Yu Qing Cheng - Santa Clara CA, US
Peter N. Glaskowsky - Cupertino CA, US
Seungyoon Peter Song - East Palo Alto CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA
Sun Microsystems Technology LTD - Hamilton

International Classification:

G06F 13/14

US Classification:

711147, 711118, 713323

Abstract:

A small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).

US Patent:

7516274, Apr 7, 2009

Filed:

Feb 9, 2006

Appl. No.:

11/351070

Inventors:

Laurent R. Moll - San Jose CA, US
Seungyoon Peter Song - East Palo Alto CA, US
Peter N. Glaskowsky - Cupertino CA, US
Yu Qing Cheng - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

711118, 711135, 710 14

Abstract:

Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.

US Patent:

7797512, Sep 14, 2010

Filed:

Oct 31, 2007

Appl. No.:

11/933297

Inventors:

Yu Qing Cheng - San Jose CA, US
John Gregory Favor - Santa Clara CA, US
Peter N. Glaskowsky - Santa Clara CA, US
Laurent R. Moll - San Jose CA, US
Carlos Puchol - Sunnyvale CA, US
Seungyoon Peter Song - Santa Clara CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/46

US Classification:

712 10, 712233

Abstract:

A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.

US Patent:

7802073, Sep 21, 2010

Filed:

Jul 23, 2007

Appl. No.:

11/781726

Inventors:

Yu Qing Cheng - Santa Clara CA, US
John Gregory Favor - Santa Clara CA, US
Carlos Puchol - Sunnyvale CA, US
Seungyoon Peter Song - San Jose CA, US
Peter Glaskowsky - Cupertino CA, US
Laurent Moll - San Jose CA, US
Joe Rowlands - Santa Clara CA, US
Donald Alpert - Phoenix AZ, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/50

US Classification:

712 10, 718 1

Abstract:

The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.

US Patent:

7899990, Mar 1, 2011

Filed:

Nov 13, 2006

Appl. No.:

11/559192

Inventors:

Laurent R. Moll - San Jose CA, US
Seungyoon Peter Song - Santa Clara CA, US
Peter N. Glaskowsky - Santa Clara CA, US
Yu Qing Cheng - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 13/00

US Classification:

711118, 711135, 710 14

Abstract:

Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

US Patent:

7904659, Mar 8, 2011

Filed:

Nov 13, 2006

Appl. No.:

11/559133

Inventors:

Laurent R. Moll - San Jose CA, US
Yu Qing Cheng - Santa Clara CA, US
Peter N. Glaskowsky - Cupertino CA, US
Seungyoon Peter Song - East Palto Alto CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 12/00

US Classification:

711135, 711146, 710 22

Abstract:

Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.

US Patent:

7958312, Jun 7, 2011

Filed:

Nov 13, 2006

Appl. No.:

11/559069

Inventors:

Laurent R. Moll - San Jose CA, US
Yu Qing Cheng - Santa Clara CA, US
Peter N. Glaskowsky - Cupertino CA, US
Seungyoon Peter Song - East Palo Alto CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 12/00

US Classification:

711135, 711146, 710 56

Abstract:

Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).