Yu-Chun Wu

US Patent:

7350177, Mar 25, 2008

Filed:

Jul 13, 2005

Appl. No.:

11/180936

Inventors:

Shine Chien Chung - Taipei Hsien, TW
Yung-Chin Hou - Taipei, TW
Kun Lung Chen - Taipei, TW
Yu-Chun Wu - Allentown PA, US

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu

International Classification:

G06F 17/50

US Classification:

716 16, 716 19

Abstract:

A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB functions as an SRAM, a second output module for generating a second output by reading at least one SRAM cell when the CLMB functions as a program logic device (PLD), wherein data on one or more bitlines coupled to the SRAM cells are controllably feeding into the first and second output modules. The configurable logic device can provide various Boolean logic functions using pass gates.

US Patent:

7401302, Jul 15, 2008

Filed:

Apr 29, 2005

Appl. No.:

11/119086

Inventors:

Kun-Lung Chen - Taipei, TW
Shine Chien Chung - Taipei Hsien, TW
Yung-Chin Hou - Taipei, TW
Yu-Chun Wu - Allentown PA, US

Assignee:

Taiwan Semiconductor Manufacturing Company Ltd. - Hsin-Chu

International Classification:

G06F 17/50

US Classification:

716 1, 716 16, 716 17

Abstract:

A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.

US Patent:

8261219, Sep 4, 2012

Filed:

Jun 4, 2008

Appl. No.:

12/133323

Inventors:

Kun-Lung Chen - Taipei, TW
Shine Chien Chung - Taipei Hsien, TW
Yung-Chin Hou - Taipei, TW
Yu-Chun Wu - Allentown PA, US

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu

International Classification:

G06F 17/50

US Classification:

716110, 716116, 716117, 716132, 716135, 716138

Abstract:

A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.

US Patent:

56338074, May 27, 1997

Filed:

May 1, 1995

Appl. No.:

8/431585

Inventors:

John P. Fishburn - Murray Hill NJ
Craig R. Kemp - Topton PA
Catherine A. Schevon - Philadelphia PA
Todd R. Seigfried - Auburn PA
Sanjiv Taneja - Berkeley Heights PA
Yu-Chun Wu - Allentown PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 1500

US Classification:

364491

Abstract:

A system and method integrate mask layout tools to automate the generation of mask layouts for fabricating an integrated circuit corresponding to an input netlist and a timing specification. The mask layout is generated by the method including the steps of automatically sizing transistors specified in the netlist, clustering the sized transistors into cells, generating a cell library, and placing-and-routing the cells to generate the mask layout. The system includes associated memory and stored programs, including a plurality of mask layout tools; and a processor operated by an automatic mask layout generation program for sequentially applying the plurality of mask layout tools to generate the mask layout from the input data. The plurality of mask layout tools includes: a transistor sizing tool for sizing transistors and to generate a netlist; a cell library generation tool for generating a cell library from the netlist; a place-and-route tool for generating the mask layout; and optionally a clustering tool for clustering the netlist generated by the transistor sizing tool into a plurality of cells.