Yuan Li

US Patent:

6351581, Feb 26, 2002

Filed:

Mar 17, 1998

Appl. No.:

09/040477

Inventors:

Christopher Richard Doerr - Middletown NJ
Yuan P. Li - Duluth GA

Assignee:

Agere Systems Optoelectronics Guardian Corp. - Orlando FL

International Classification:

G02B 626

US Classification:

385 24, 359124

Abstract:

An optical add-drop multiplexer (ADM) avoids waveguide crossings by being constructed in the form of a Mach-Zehnder interferometer having a demultiplexer/multiplexer (demux/mux) pair in each of its arms. Each demux/mux pair is interconnected by coherent connecting paths having heating elements for increasing the path length of selected connecting paths. Waveguide optical couplers having asymmetric transfer functions are used at the input and output of the ADM. These couplers cooperate with the activated heating elements to add and/or delete a selected optical channel to/from an optical transmission path. Each coherent connecting path includes a number of waveguides. The end-to-end transmission characteristic of the ADM through each individual waveguide has a Gaussian shape. These Gaussian shapes are designed intersect at their -3 dB wavelengths so that the end-to-end transmission characteristic of the ADM is flat.

US Patent:

6888238, May 3, 2005

Filed:

Jul 9, 2003

Appl. No.:

10/616858

Inventors:

Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L023/34

US Classification:

257706

Abstract:

A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 22 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A heat spreader having parallel channels on opposite sides is attached to the chip carrier along the channels. The heat spreader has a second coefficient of thermal expansion that is smaller than or equal to the coefficient of thermal expansion of the chip carrier. The interplay between the heat spreader and the chip carrier can effectively reduce package warpage and maintain coplanarity within the specification.

US Patent:

6909176, Jun 21, 2005

Filed:

Nov 20, 2003

Appl. No.:

10/719451

Inventors:

Wen-Chou Vincent Wang - Cupertino CA, US
Donald S. Fritz - San Jose CA, US
Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L023/10

US Classification:

257706, 257701, 257783, 257775

Abstract:

Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

US Patent:

6949404, Sep 27, 2005

Filed:

Nov 25, 2002

Appl. No.:

10/305671

Inventors:

Don Fritz - San Jose CA, US
Wen-chou Vincent Wang - Cupertino CA, US
Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L021/44
H01L021/48
H01L021/50

US Classification:

438106, 438107, 438108, 438125

Abstract:

Provided are a semiconductor flip chip package with warpage control and fabrication methods for such packages. The packages of the present invention include heat spreader lids that are rigidly attached to the die or packaging substrate with a bond that can withstand the considerable bowing pressures caused by the CTE mismatch between the die and substrate. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the PCB board to which it is ultimately bound. Package reliability is thereby also enhanced, particularly for large die sizes.

US Patent:

7009307, Mar 7, 2006

Filed:

May 19, 2004

Appl. No.:

10/849651

Inventors:

Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257783, 257707, 438118

Abstract:

Provided are a semiconductor die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the die and packaging substrate. In general, the modulus of the adhesive, which is used to attach the heat spreader to the substrate, is selected to provide a relatively “soft” connection. The result is a package with less bowing and so improved co-planarity (e. g. , in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the die and package reliabilities are thereby enhanced.

US Patent:

7144756, Dec 5, 2006

Filed:

May 10, 2005

Appl. No.:

11/126571

Inventors:

Wen-Chou Vincent Wang - Cupertino CA, US
Donald S. Fritz - San Jose CA, US
Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01I 21/44

US Classification:

438106, 257E23001

Abstract:

Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

US Patent:

7300822, Nov 27, 2007

Filed:

Apr 28, 2005

Appl. No.:

11/118630

Inventors:

Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 21/00

US Classification:

438122, 257706

Abstract:

A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 22 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A heat spreader having parallel channels on opposite sides is attached to the chip carrier along the channels. The heat spreader has a second coefficient of thermal expansion that is smaller than or equal to the coefficient of thermal expansion of the chip carrier. The interplay between the heat spreader and the chip carrier can effectively reduce package warpage and maintain coplanarity within the specification.

US Patent:

7427813, Sep 23, 2008

Filed:

Nov 20, 2003

Appl. No.:

10/719218

Inventors:

Wen-chou Vincent Wang - Cupertino CA, US
Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 29/40
H01L 23/28
H01L 23/29

US Classification:

257790, 257643, 257787, 257656, 257727, 257734

Abstract:

Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).