Zhi Zhang

US Patent:

20130151789, Jun 13, 2013

Filed:

Dec 13, 2011

Appl. No.:

13/323938

Inventors:

Tsai-Yang Jea - Poughkeepsie NY, US
Zhi Zhang - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/08

US Classification:

711141, 711E12026

Abstract:

A method, system or computer usable program product for managing a cache region including receiving a new region to be stored within the cache, the cache including multiple regions defined by one or more ranges having a starting index and an ending index, and storing the new region in the cache in accordance with a cache invariant, the cache invariant ensuring that regions in the cache are not overlapping and that the regions are stored in a specified order.

US Patent:

20130152101, Jun 13, 2013

Filed:

Dec 8, 2011

Appl. No.:

13/314477

Inventors:

Tsai-Yang Jea - Poughkeepsie NY, US
William P. LePera - Poughkeepsie NY, US
Hanhong Xue - Wappingers Falls NY, US
Zhi Zhang - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/50

US Classification:

718104

Abstract:

A job may be divided into multiple tasks that may execute in parallel on one or more compute nodes. The tasks executing on the same compute node may be coordinated using barrier synchronization. However, to perform barrier synchronization, the tasks use (or attach) to a barrier synchronization register which establishes a common checkpoint for each of the tasks. A leader task may use a shared memory region to publish to follower tasks the location of the barrier synchronization register—i.e., a barrier synchronization register ID. The follower tasks may then monitor the shared memory to determine the barrier synchronization register ID. The leader task may also use a count to ensure all the tasks attach to the BSR. This advantageously avoids any task-to-task communication which may reduce overhead and improve performance.

US Patent:

20130152103, Jun 13, 2013

Filed:

Dec 7, 2012

Appl. No.:

13/707621

Inventors:

International Business Machines Corporation - Armonk NY, US
William P. LEPERA - Poughkeepsie NY, US
HanHong XUE - Wappingers Falls NY, US
Zhi ZHANG - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/52

US Classification:

718104

Abstract:

A job may be divided into multiple tasks that may execute in parallel on one or more compute nodes. The tasks executing on the same compute node may be coordinated using barrier synchronization. However, to perform barrier synchronization, the tasks use (or attach) to a barrier synchronization register which establishes a common checkpoint for each of the tasks. A leader task may use a shared memory region to publish to follower tasks the location of the barrier synchronization register—i.e., a barrier synchronization register ID. The follower tasks may then monitor the shared memory to determine the barrier synchronization register ID. The leader task may also use a count to ensure all the tasks attach to the BSR. This advantageously avoids any task-to-task communication which may reduce overhead and improve performance.

US Patent:

20130247069, Sep 19, 2013

Filed:

Mar 15, 2012

Appl. No.:

13/420676

Inventors:

Wen Chen - Shanghai, CN
Tsai-Yang Jea - Poughkeepsie NY, US
William P. Lepera - Poughkeepsie NY, US
Serban C. Maerean - Ridgefield CT, US
Hung Q. Thai - Bronx NY, US
Hanhong Xue - Wappingers Falls NY, US
Zhi Zhang - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 9/46

US Classification:

718107

Abstract:

In a parallel computer executing a parallel application, where the parallel computer includes a number of compute nodes, with each compute node including one or more computer processors, the parallel application including a number of processes, and one or more of the processes executing a barrier operation, creating a checkpoint of a parallel application includes: maintaining, by each computer processor, global barrier operation state information, the global barrier operation state information includes an aggregation of each process's barrier operation state information; invoking, for each process of the parallel application, a checkpoint handler; saving, by each process's checkpoint handler as part of a checkpoint for the parallel application, the process's barrier operation state information; and exiting, by each process, the checkpoint handler.

US Patent:

20160034312, Feb 4, 2016

Filed:

Jul 29, 2014

Appl. No.:

14/445546

Inventors:

- Armonk NY, US
Tsai-Yang Jea - Poughkeepsie NY, US
Wiliam P. LePera - Poughkeepsie NY, US
Hung Q. Thai - Bronx NY, US
Hanhong Xue - Wappingers Falls NY, US
Zhi Zhang - Poughkeepsie NY, US

International Classification:

G06F 9/50
G06F 9/52
G06F 11/34
G06F 9/46

Abstract:

A method, apparatus and program product utilize an empirical approach to determine the locations of one or more IO adapters in an HPC environment. Performance tests may be run using a plurality of candidate mappings that map IO adapters to various locations in the HPC environment, and based upon the results of such testing, speculative adapter affinity information may be generated that assigns one or more IO adapters to one or more locations to optimize adapter affinity performance for subsequently-executed tasks.

US Patent:

20160034313, Feb 4, 2016

Filed:

Oct 31, 2014

Appl. No.:

14/530095

Inventors:

- Armonk NY, US
Tsai-Yang Jea - Poughkeepsie NY, US
Wiliam P. LePera - Poughkeepsie NY, US
Hung Q. Thai - Bronx NY, US
Hanhong Xue - Wappingers Falls NY, US
Zhi Zhang - Poughkeepsie NY, US

International Classification:

G06F 9/50
G06F 9/46
G06F 9/52
G06F 11/34

Abstract:

A method, apparatus and program product utilize an empirical approach to determine the locations of one or more IO adapters in an HPC environment. Performance tests may be run using a plurality of candidate mappings that map IO adapters to various locations in the HPC environment, and based upon the results of such testing, speculative adapter affinity information may be generated that assigns one or more IO adapters to one or more locations to optimize adapter affinity performance for subsequently-executed tasks.

US Patent:

20140089601, Mar 27, 2014

Filed:

Nov 28, 2013

Appl. No.:

14/093036

Inventors:

- Armonk NY, US
Zhi Zhang - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/08

US Classification:

711141

Abstract:

A method for managing a cache region including receiving a new region to be stored within the cache, the cache including multiple regions defined by one or more ranges having a starting index and an ending index, and storing the new region in the cache in accordance with a cache invariant, the cache invariant ensuring that regions in the cache are not overlapping and that the regions are stored in a specified order.