Zhigang G Han

US Patent:

7111186, Sep 19, 2006

Filed:

Apr 28, 2003

Appl. No.:

10/425213

Inventors:

Zhigang Han - Sunnyvale CA, US
Cong Khieu - San Jose CA, US
Kailashnath Nagarakanti - Santa Clara CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1/12

US Classification:

713500, 713400

Abstract:

A CPU clock signal generated from a phase lock loop (PLL) circuit and a feedback signal of the PLL circuit are used in generating a JBUS clock signal. The CPU clock signal and the feedback signal include the same amount of static phase offset introduced by the PLL circuit. The CPU clock signal and the feedback signal are input to an alignment detection circuit and used in generating the JBUS clock signal. In one embodiment, the JBUS clock signal is generated in synchronization with the CPU clock signal and having the frequency of the feedback signal. The present invention reduces or eliminates misalignment of the leading edge of the JBUS signal with reference to a specific leading edge of the CPU clock signal due to the presence of static phase offset introduced by the PLL circuit.

US Patent:

20030108109, Jun 12, 2003

Filed:

Dec 10, 2001

Appl. No.:

10/014301

Inventors:

Cong Khieu - San Jose CA, US
Zhigang Han - Pasadena CA, US

International Classification:

H04B003/00
H04L025/00

US Classification:

375/257000

Abstract:

A method and system for reducing coupling capacitance interference between adjacent transmission lines in an electrical circuit. The method and system includes the use of inverter and buffer devices that are laid out along signal paths carrying signal transmissions to assure that a portion of signal transmission between devices has zero coupling capacitance, yet provides for a net coupling capacitance of one.

US Patent:

20030169081, Sep 11, 2003

Filed:

Mar 5, 2002

Appl. No.:

10/090894

Inventors:

Zhigang Han - San Jose CA, US
Cong Khieu - San Jose CA, US

International Classification:

H03B001/00

US Classification:

327/108000

Abstract:

The present invention describes a method and apparatus to reduce the delay variations caused by the process variations in DDR input buffers. The changes in the impedance due to the process variations are used to determine the bias current for the DDR buffers. The bias current is proportional to the changes in the impedance. The bias current is adjusted to maintain small delay variations in the DDR buffers. The delays in the DDR buffers can be adjusted by adjusting the bias current in response to the corresponding impedance changes due to the process variations in the semiconductor devices.

US Patent:

6511859, Jan 28, 2003

Filed:

Mar 10, 2000

Appl. No.:

09/523399

Inventors:

Fukang Jiang - Pasadena CA
Zhigang Han - Pasadena CA
Yu-Chong Tai - Pasadena CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01L 2100

US Classification:

438 48, 438 24, 438 50, 438 52, 438 53, 438691, 438619, 438635

Abstract:

A combined IC/Mems process forms the IC parts first, and then forms the MEMS parts. One option forms a parylene overlayer, then forms a cavity under the parylene overlayer.