Zong W Yu

US Patent:

6466825, Oct 15, 2002

Filed:

Aug 10, 2001

Appl. No.:

09/927717

Inventors:

Yuanlong Wang - Sunnyvale CA
Zong Yu - Cupertino CA
Xiaofan Wei - Sunnyvale CA
Earl T. Cohen - Fremont CA
Brian R. Baird - Pleasanton CA
Daniel Fu - Sunnyvale CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G05B 1918

US Classification:

700 5, 710146, 711110, 711 14

Abstract:

A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both bus-based based and point-to-point control of the target devices.

US Patent:

62927051, Sep 18, 2001

Filed:

Sep 29, 1998

Appl. No.:

9/163294

Inventors:

Yuanlong Wang - Sunnyvale CA
Zong Yu - Cupertino CA
Xiaofan Wei - Sunnyvale CA
Earl T. Cohen - Fremont CA
Brian R. Baird - Pleasanton CA
Daniel Fu - Sunnyvale CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G05B 1918

US Classification:

700 5

Abstract:

A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both busbased and point-to-point control of the target devices.