Benjamin D Cook

US Patent:

20220406649, Dec 22, 2022

Filed:

Feb 25, 2022

Appl. No.:

17/681029

Inventors:

- Dallas TX, US
Scott Robert SUMMERFELT - Garland TX, US
Benjamin COOK - Los Gatos CA, US

International Classification:

H01L 21/762
H01L 21/768
H01L 21/02
H01L 27/01

Abstract:

An integrated circuit (IC) includes a semiconductor substrate and an interconnect region. The semiconductor substrate has a first surface and a second surface opposite the first surface. The semiconductor substrate has a first region with a passive component. The semiconductor substrate has a second region outside the first region. The resistance of the second region is smaller than the resistance of the first region. The interconnection region is on the second surface of the semiconductor substrate.

US Patent:

20220406738, Dec 22, 2022

Filed:

Apr 29, 2022

Appl. No.:

17/732822

Inventors:

- Dallas TX, US
Adam FRUEHLING - Garland TX, US
Baher HAROUN - Allen TX, US
Scott Robert SUMMERFELT - Garland TX, US
Benjamin Stassen COOK - Los Gatos CA, US

International Classification:

H01L 23/66
H01Q 1/22
H01Q 9/04

Abstract:

An integrated circuit (IC) includes a semiconductor substrate having a first surface and a second surface opposite the first surface. A through wafer trench (TWT) extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate. Dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region has a conductive transmit patch. An antenna is formed, at least in part, by the dielectric material in the TWT and the transmit patch in the interconnect region. The antenna is configured to transmit or receive electromagnetic radiation between the transmit patch and the second surface of the semiconductor substrate through the dielectric material within the trench.

US Patent:

20220406956, Dec 22, 2022

Filed:

Feb 25, 2022

Appl. No.:

17/680981

Inventors:

- Dallas TX, US
Baher HAROUN - Allen TX, US
Gerd SCHUPPENER - Allen TX, US
Scott Robert SUMMERFELT - Garland TX, US
Benjamin COOK - Los Gatos CA, US

International Classification:

H01L 31/173
H01L 49/02

Abstract:

An integrated circuit (IC) includes a substrate having a first surface and a second surface opposite the first surface. The substrate has a first region containing a first circuit and a second region containing a second circuit. The first circuit operates at a first supply voltage. The second circuit operates at a second supply voltage. The second supply voltage is higher than the first supply voltage. The IC includes a through wafer trench (TWT) extending from the first surface of the substrate to the second surface of the semiconductor substrate. The TWT separates the first region from the second region. A dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region is continuous over the first region, the second region, and the TWT. A non-galvanic communication channel is between the first and second circuits.

US Patent:

20220250909, Aug 11, 2022

Filed:

Apr 26, 2022

Appl. No.:

17/729121

Inventors:

- Dallas TX, US
Nazila DADVAND - Richardson TX, US
Benjamin Stassen COOK - Addison TX, US
Archana VENUGOPAL - Dallas TX, US

International Classification:

C01B 21/064
C23C 16/34
C23C 18/32
C23C 18/16
C23C 18/36
C23C 18/28
C23C 18/30
C23C 18/20

Abstract:

A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.

US Patent:

20220252637, Aug 11, 2022

Filed:

Apr 28, 2022

Appl. No.:

17/732475

Inventors:

- Dallas TX, US
Benjamin Stassen COOK - Addison TX, US

International Classification:

G01P 21/00
G01P 15/09

Abstract:

A method includes measuring a temperature of a semiconductor die, in which the semiconductor die includes a piezoelectric device, a pyroelectric device, and a memory. The method further includes receiving a first signal from the pyroelectric device, and based on the first signal, determining a parameter to be combined with a second signal from the piezoelectric device. The method further includes storing the parameter and the measured temperature into the memory.

US Patent:

20220221353, Jul 14, 2022

Filed:

Nov 30, 2021

Appl. No.:

17/538782

Inventors:

- Dallas TX, US
Baher S. HAROUN - Allen TX, US
Benjamin Stassen COOK - Los Gatos CA, US
Sreenivasan Kalyani KODURI - Dallas TX, US
Michael SZELONG - Freising, DE
Ernst MUELLNER - Muenchen, DE

International Classification:

G01L 1/18
H01L 23/31
H01L 23/495

Abstract:

A force sensor including a semiconductor die, and a die pad coupled to the semiconductor die, the semiconductor die configured to detect a force in the die pad. In addition, the force sensor includes a mold compound covering the semiconductor die and having an outer perimeter, a first side, and a second side opposite the first side, the outer perimeter extending between the first side and the second side, the die pad exposed out of the mold compound along the first side. Further, the force sensor includes a mounting frame engaged with the die pad along the second side of the mold compound, the mounting frame including multiple mounting pads extended outward in multiple directions from the outer perimeter.

US Patent:

20220223486, Jul 14, 2022

Filed:

Nov 30, 2021

Appl. No.:

17/538850

Inventors:

- Dallas TX, US
Baher S. HAROUN - Allen TX, US
Benjamin Stassen COOK - Los Gatos CA, US
Michael SZELONG - Freising, DE
Ernst MUELLNER - Muenchen, DE
Jeronimo SEGOVIA-FERNANDEZ - San Jose CA, US

International Classification:

H01L 23/13
H01L 23/31
H01L 23/495
G01L 1/18

Abstract:

An example semiconductor package includes a semiconductor die configured to detect a force. In addition, the semiconductor package includes a mold compound covering the semiconductor die. Further, the semiconductor package includes an engagement surface including a pattern of projections adapted to engage with a mounting surface on a member of interest.

US Patent:

20230093214, Mar 23, 2023

Filed:

Nov 29, 2022

Appl. No.:

18/059473

Inventors:

- Dallas TX, US
Benjamin Stassen COOK - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/14
H01L 21/48
H01L 23/498
H01L 21/78

Abstract:

An integrated circuit comprises a substrate including a shape memory polymer, and a semiconductor die mounted on the substrate.