Bryan Keith Robbins

US Patent:

6671838, Dec 30, 2003

Filed:

Sep 27, 2000

Appl. No.:

09/671413

Inventors:

Timothy J. Koprowski - Newburgh NY
Mary P. Kusko - Hopewell Junction NY
Lawrence K. Lange - Wappingers Falls NY
Bryan J. Robbins - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 2900

US Classification:

714726, 714718, 324765, 365201, 365221

Abstract:

An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.

US Patent:

6836865, Dec 28, 2004

Filed:

Oct 9, 2001

Appl. No.:

09/973398

Inventors:

Mary P. Kusko - Hopewell Junction NY
William V. Huott - Holmes NY
Bryan J. Robbins - Poughkeepsie NY
Timothy Charest - West Hurley NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714726, 714729, 714728, 714727

Abstract:

A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.

US Patent:

6990076, Jan 24, 2006

Filed:

May 18, 1999

Appl. No.:

09/313261

Inventors:

Timothy G. McNamara - Fishkill NY, US
Bryan J. Robbins - Poughkeepsie NY, US
William R. Reohr - Bronx NY, US

International Classification:

H04J 15/00

US Classification:

370241, 714726

Abstract:

At least one swapper circuit is electrically connected to a bus between a plurality of entities sharing the bus. The swapper comprises a pair of series connected latches and a tristate circuits, one for each data direction, connected in parallel. The swapper acts as a revolving door, capturing data traveling from either side of the bus and shuffling the data to the other side without collision. A latch circuit is connected at either end of the bus for capturing data arriving from the other side. In addition, each of the drive entities is provided with a master/slave latched equipped with scan-in/scan-out ports, respectively, to enable testing of the circuit by allowing internal nodes of the circuit to be observed without requiring an external connection for each node accessed. In a VLSI arrangement, the scan-in/scan-out ports are connected together from a plurality of such circuits such that a variety of test patterns for various hardware configurations may be realized.

US Patent:

7117415, Oct 3, 2006

Filed:

Jan 15, 2004

Appl. No.:

10/757781

Inventors:

Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
William J. Hurley - Poughkeepsie NY, US
Bryan J. Robbins - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714733, 714736

Abstract:

Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e. g. , logical BIST, array BIST, etc. ) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.

US Patent:

7921346, Apr 5, 2011

Filed:

Oct 31, 2008

Appl. No.:

12/262976

Inventors:

Donato Orazio Forlenza - Hopewell Junction NY, US
Orazio Pasquale Forlenza - Hopewell Junction NY, US
Bryan J. Robbins - Beavercreek OH, US
Phong T. Tran - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714733, 714 30, 714 36, 714718, 714724, 714726, 714727, 714729, 714734, 714738, 714741, 365200, 365201, 36518501, 711102, 711103, 716 4, 716 18

Abstract:

A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.

US Patent:

7934134, Apr 26, 2011

Filed:

Jun 5, 2008

Appl. No.:

12/133830

Inventors:

Donato O. Forlenza - Hopewell Junction NY, US
Orazio P. Forlenza - Hopewell Junction NY, US
Bryan J. Robbins - Beavercreek OH, US
Phong T. Tran - Highland NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714733, 714726, 714727, 714729, 714734

Abstract:

A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

US Patent:

8095837, Jan 10, 2012

Filed:

Mar 19, 2008

Appl. No.:

12/051744

Inventors:

Mary P. Kusko - Hopewell Junction NY, US
Barry W. Krumm - Poughkeepsie NY, US
Patrick Meaney - Poughkeepsie NY, US
Bryan J. Robbins - Beavercreek OH, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

A test method and apparatus for randomly testing logic structures. The method includes identifying and analyzing a functional behavior of a logic structure to be covered during the random testing, modifying the logic structure such that the logic structure behaves in a functional manner during random testing, and generating patterns to exercise the modified logic structure.

US Patent:

63145405, Nov 6, 2001

Filed:

Apr 12, 1999

Appl. No.:

9/290516

Inventors:

William V. Huott - Holmes NY
Mary P. Kusko - Hopewell Junction NY
Gregory O'Malley - Essex Junction VT
Bryan J. Robbins - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128
G06F 1100

US Classification:

714738

Abstract:

A partitioned pseudo-random logic test (PRLT) for integrated circuit chips for improving manufacturability is disclosed. The technique makes available previously difficult-to-collect empirical data to accurately improve test effectiveness while significantly lowering test time and test cost. An embodiment includes a method for testing IC chips, including generating values for latches for a complete test pattern set, partitioning the test pattern set into a plurality of partitioned test pattern subsets, and running the subsets against a chip. Another embodiment is directed to a system that tests IC chips, having a latch value generator that generates values for latches for a complete test pattern set, a test pattern divider that partitions the complete test pattern set into a plurality of partitioned test pattern subsets, and a tester that runs the partitioned test pattern subsets against the chip.