Charles A Hartman

US Patent:

7467252, Dec 16, 2008

Filed:

Jul 29, 2003

Appl. No.:

10/629940

Inventors:

Charles Hartman - Fort Collins CO, US
Raphael Gay - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/00
G06F 13/36
G03G 15/01

US Classification:

710316, 710302, 710306, 710311, 399301

Abstract:

An I/O bus architecture is configurable so that I/O bandwidth may be re-allocated from one I/O slot or device to another. A first intermediate bus couples a system bus interface device to a first I/O bus interface device. A second intermediate bus couples the system bus interface device to a switching device. The switching device functions to couple the second intermediate bus either to the first or to the second I/O bus interface device responsive to a steering signal. The steering signal may be configured to indicate whether or not an I/O device is coupled to the second I/O bus interface device. If so, then the second intermediate bus is coupled to the second I/O bus interface device; but if not, it is coupled to the first I/O bus interface device so that the first I/O bus interface device may utilize the extra I/O bandwidth not being used by the second I/O bus interface device.

US Patent:

20110179212, Jul 21, 2011

Filed:

Jan 20, 2010

Appl. No.:

12/690819

Inventors:

Charles Andrew Hartman - Ft Collins CO, US

International Classification:

G06F 13/36

US Classification:

710309

Abstract:

Systems and methods of bus arbitration for sideband signals in a multichip system are disclosed. An exemplary method comprises packaging at least one sideband signal as a micropacket. The method also comprises holding the micropacket in an outgoing sideband register. The method also comprises monitoring a bus for a quiescent state, the bus having a plurality of links to other chips in the multichip system. The method also comprises issuing the micropacket from the outgoing sideband register if the bus is in a quiescent state.

US Patent:

20180089358, Mar 29, 2018

Filed:

Sep 29, 2016

Appl. No.:

15/280906

Inventors:

- Houston TX, US
Karl J. Bois - Fort Collins CO, US
Charles Andrew Hartman - Fort Collins CO, US

International Classification:

G06F 17/50

Abstract:

Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.