Sandip Kundu - Austin TX, US Sanjay Sengupta - San Jose CA, US Dhiraj Goswami - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/28 G01R 31/30 G06F 11/00 G07F 11/00
US Classification:
714741, 714 33, 714 37, 714745
Abstract:
A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.
Generating Responses To Patterns Stimulating An Electronic Circuit With Timing Exception Paths
Improved responses can be generated to scan patterns (e. g. , test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
Generating Responses To Patterns Stimulating An Electronic Circuit With Timing Exception Paths
Improved responses can be generated to scan patterns (e. g. , test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.
Adaptive State-To-Symbolic Transformation In A Canonical Representation
Dhiraj Goswami - Wilsonville OR, US Ngai Ngai William Hung - San Jose CA, US Jasvinder Singh - San Jose CA, US Qiang Qiang - Santa Clara CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716100
Abstract:
Some embodiments provide a system for adaptively performing state-to-symbolic transformation in a canonical representation which is used for generating random stimulus for a constrained-random simulation. The system can construct a canonical representation for a set of constraints using the set of random variables and the subset of the state variables in the constraints. Next, the system can use the canonical representation to generate random stimulus for the constrained-random simulation, and monitor parameters associated with the constrained-random simulation. Next, the system can add state variables to or remove state variables from the canonical representation based at least on the monitored parameters. The system can then use the modified canonical representation which has a different set of state variables to generate random stimulus for the constrained-random simulation.
Method And Apparatus For Constructing A Canonical Representation
Ngai Ngai William Hung - San Jose CA, US Dhiraj Goswami - Wilsonville OR, US Jasvinder Singh - San Jose CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 15/18
US Classification:
706 12, 716122
Abstract:
Some embodiments provide systems and techniques to facilitate construction of a canonical representation (CR) which represents a logical combination of a set of logical functions. During operation, the system can receive a CR-size limit. Next, the system can construct a set of CRs based on the set of logical functions, wherein each CR in the set of CRs represents a logical function in the set of logical functions. The system can then combine a subset of the set of CRs to obtain a combined CR. Next, the system can identify a problematic CR which when combined with the combined CR causes the CR-size limit to be exceeded. The system can then report the problematic CR and/or a logical function associated with the problematic CR to a user, thereby helping the user to identify an error in the set of logical functions.
Performing Implication And Decision Making Using Multiple Value Systems During Constraint Solving
Qiang Qiang - Santa Clara CA, US Dhiraj Goswami - Wilsonville OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716106, 716136
Abstract:
Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. An embodiment can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. Next, the embodiment can generate a circuit model based on the set of constraints, wherein assignable values for at least one node in the circuit model are represented in multiple value systems. The embodiment can then assign random values to the set of random variables based on the circuit model.
Technique For Honoring Multi-Cycle Path Semantics In Rtl Simulation
Kaushik De - Bangalore, IN Badri P. Gopalan - Santa Clara CA, US Dhiraj Goswami - Wilsonville OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716106, 716132, 716136
Abstract:
An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.
Simulation-Based Technique For Contention Avoidance In Automatic Test Pattern Generation
Sandip Kundu - Austin TX, US Saniay Sengupta - San Jose CA, US Dhiraj Goswami - Mountain View CA, US
Assignee:
Intel Corporation
International Classification:
G06F017/50 G06F009/45
US Classification:
716/004000, 716/005000
Abstract:
A technique for finding contention-free states for contention-causing multiply driven nodes in an integrated circuit device to form a contention-free structural test pattern. The technique includes identifying multiply driven nodes having potential for causing contention by applying a predetermined number of random state assignments to the integrated circuit device. A scan group is identified using the identified contention-causing multiply driven nodes. Independent scan groups (ISGs) are created by identifying common elements in the identified scan groups and merging the identified scan groups to create ISGs. Contention-free states are found for each of the created scan groups.
Cadence Design Systems
Vice President, Ml and Dl and Emerging Technologies
Synopsys Apr 1, 2007 - Aug 2018
Fellow, R and D Technology and Operational Leader, R and D Head of Zebu Software Development
Mentor Graphics Sep 2003 - Mar 2007
Research Staff Engineer
Intel Corporation Dec 1999 - Sep 2003
Manager, Design Automation Flow
Synopsys May 1997 - Dec 1999
Senior Software Engineer
Education:
University of Southern California 1996 - 1997
Master of Science, Masters, Computer Engineering
Indian Institute of Technology, Kanpur 1993 - 1994
Masters, Master of Technology, Electrical Engineering
Indian Institute of Technology, Kanpur 1988 - 1992
Cotton College 1986 - 1988
Skills:
Algorithms Eda Simulations Verilog Engineering Management Programming Multithreading Linux Unix Rtl Design Program Management Microprocessors Firmware Xilinx C/C++ Stl Assembly Language Process Improvement Strategic Planning Debugging Integrated Circuits Soc Asic C Software Architecture/Systems Application Specific Integrated Circuits