Huy Q Luong

US Patent:

6728908, Apr 27, 2004

Filed:

Nov 20, 2000

Appl. No.:

09/717800

Inventors:

Ryan Fukuhara - Torrance CA
Leonard Day - Pasadena CA
Huy H. Luong - San Marino CA
Robert Rasmussen - Monrovia CA
Savio N. Chau - Hacienda Heights CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

G06F 1100

US Classification:

714 48, 714 43, 716 4

Abstract:

In an embodiment, a bus controller for connecting a device to an Inter-Integrated Circuit (I2C) bus includes fault tolerance features. The I2C bus controller may support fail silent, cyclic redundancy check (CRC), and byte count check operations. The I2C bus controller may include a control unit connected to an I2C core module having a base address. The I2C bus controller may also include a second I2C core module having a base address plus one (BP ). The I2C bus controller may also include a mute timer that countdowns a mute timeout period. This mute timer may be reset upon receiving a fail silent test message sent by a master on the I2C bus in slave mode, or, in the master mode, from itself through the BP I2C core module. If the mute timeout period expires, the control unit may disable the I2C bus controller from transmitting on the I2C bus. The control unit may format CRC values and byte count values into messages, and include a byte counter to compare actual bytes received to the expected byte count indicated by a received byte count value.

US Patent:

57905673, Aug 4, 1998

Filed:

Aug 28, 1995

Appl. No.:

8/519786

Inventors:

Gary S. Bolotin - Moneovia CA
James A. Donaldson - Glendale CA
Huy H. Luong - Alhambra CA
Steven H. Wood - Los Angeles CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H03M 1300
H04B 7204
H04B 7185
H04J 324

US Classification:

371 3701

Abstract:

An uplink controlling assembly speeds data processing using a special parallel codeblock technique. A correct start sequence initiates processing of a frame. Two possible start sequences can be used; and the one which is used determines whether data polarity is inverted or non-inverted. Processing continues until uncorrectable errors are found. The frame ends by intentionally sending a block with an uncorrectable error. Each of the codeblocks in the frame has a channel ID. Each channel ID can be separately processed in parallel. This obviates the problem of waiting for error correction processing. If that channel number is zero, however, it indicates that the frame of data represents a critical command only. That data is handled in a special way, independent of the software. Otherwise, the processed data further handled using special double buffering techniques to avoid problems from overrun.

US Patent:

57905681, Aug 4, 1998

Filed:

Jan 31, 1996

Appl. No.:

8/594728

Inventors:

Huy H. Luong - Alhambra CA
James A. Donaldson - Glendale CA
Steven H. Wood - Los Angeles CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

G03M 1300

US Classification:

371 371

Abstract:

Apparatus and method for providing downlink frames to be transmitted from a spacecraft to a ground station. Each downlink frame includes a synchronization pattern and a transfer frame. The apparatus may comprise a monolithic Reed-Solomon downlink (RSDL) encoding chip coupled to data buffers for storing transfer frames. The RSKL chip includes a timing device, a bus interface, a timing and control unit, a synchronization pattern unit, and a Reed-Solomon encoding unit, and a bus arbiter.