Zhi-Yuan Wu - Union City CA, US Jia Feng - San Jose CA, US Juhi Bansal - Sunnyvale CA, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
G06F 17/50
US Classification:
716112, 716111
Abstract:
An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.
James D. Plummer - Portola Valley CA, US Peter B. Griffin - Woodside CA, US Jia Feng - Palo Alto CA, US
International Classification:
H01L 21/208 H01L 21/20
US Classification:
438481, 438502, 438478, 257E21114, 257E2109
Abstract:
Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location. The relatively small physical opening and/or the change in crystalline front direction may be implemented, for example, using a material that is substantially unreactive with the liquid-phase material to contain the crystalline growth.
Modeling Gate Transconductance In A Sub-Circuit Transistor Model
Jia Feng - San Jose CA, US Zhi-Yuan Wu - Union City CA, US Juhi Bansal - Sunnyvale CA, US Srinath Krishnan - Campbell CA, US
Assignee:
GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:
G06F 17/50 G06F 17/10
US Classification:
703 2
Abstract:
A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.
Recommending Virtual Reward Offers And Awarding Virtual Rewards
Linda TONG - San Francisco CA, US Stephen James McCARTHY - San Francisco CA, US Ryan Allen JOHNS - San Francisco CA, US Hai-Van PHAM - Milpitas CA, US Norman CHAN - Belmont CA, US Amir Bashir MANJI - San Francisco CA, US Jia Feng - San Francisco CA, US Marc BOURGET - Mountain View CA, US Joey PAN - Fremont CA, US
International Classification:
G06Q 30/02
US Classification:
705 1431, 705 1427
Abstract:
In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.
Methods For Fabricating Integrated Circuits With Drift Regions And Replacement Gates
Jia Feng - San Jose CA, US Kuldeep Amarnath - San Jose CA, US Kevin J. Yang - Santa Clara CA, US
Assignee:
GLOBALFOUNDRIES INC. - Grand Cayman
International Classification:
H01L 21/336
US Classification:
438286, 257E21417
Abstract:
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.
Constrained Motion Field Estimation For Hardware Efficiency
Decoding a current block of a current frame includes obtaining motion trajectories between the current frame and at least one previously coded frame by projecting motion vectors from the at least one previously coded frame onto the current frame. A motion field is obtained between the current frame and a reference frame used for coding the current frame. The motion field is obtained by extending the motion trajectories from the current frame towards the reference frame. A motion vector for the current block is identified based on the motion field. A prediction block is obtained for the current block using a reference block of the reference frame identified using the motion vector.
Systems, Apparatus, And Methods For Enhanced Image Capture
- Mountain View CA, US Damien Kelly - Mountain View CA, US Xiaoying He - Mountain View CA, US Jia Feng - Mountain View CA, US Bartlomiej Wronski - Mountain View CA, US Peyman Milanfar - Mountain View CA, US Lucian Ion - Mountain View CA, US
International Classification:
G06T 3/40 B60R 11/04 G06F 17/18 G06F 17/16
Abstract:
Described examples relate to an apparatus comprising one or more image sensors coupled to a vehicle and at least one processor. The at least one processor may be configured to capture, in a burst sequence using the one or more image sensors, multiple frames of an image of a scene, the multiple frames having respective, relative offsets of the image across the multiple frames and perform super-resolution computations using the captured, multiple frames of the image of the scene. The at least one processor may also be configured to accumulate, based on the super-resolution computations, color planes and combine, using the one or more processors, the accumulated color planes to create a super-resolution image of the scene.
- Walldorf, DE Jia Feng - Pleasanton CA, US Alexander Chernavin - San Carlos CA, US Chitong Chung - Mountain View CA, US Shyam Sunder Reddy Avula - San Ramon CA, US Xin Guo - Fremont CA, US Scott Hamilton - Aldie VA, US Clay Jacobs - Hillsborough CA, US Christopher de Castro - Farmington MN, US Kaushik Ghosh - Santa Clara CA, US
International Classification:
G06F 3/06
Abstract:
A distributed storage system includes a primary storage system and a secondary storage system. The secondary storage system stores the actual data and the primary storage system stores metadata for the actual data. The metadata references at the primary storage system may be deleted without deleting the corresponding data at the secondary storage system. Snapshots of the metadata at the primary storage system are sent to the secondary storage system. The secondary storage system can compare two metadata snapshots received from the primary storage in order to determine whether data stored at the secondary storage system has been deleted at the primary storage system for longer than a retention period. Such data may be deleted to free up storage space at the secondary storage server.