Lap Chow Chan

US Patent:

6348385, Feb 19, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/726256

Inventors:

Randall Cher Liang Cha - Singapore, SG
Tae Jong Lee - Singapore, SG
Alex See - Singapore, SG
Lap Chan - San Francisco CA
Chee Tee Chua - Singapore, SG

Assignee:

Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 21336

US Classification:

438287, 438563, 438591

Abstract:

The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.

US Patent:

6355563, Mar 12, 2002

Filed:

Mar 5, 2001

Appl. No.:

09/798652

Inventors:

Randall Cher Liang Cha - Singapore, SG
Alex See - Singapore, SG
Yeow Kheng Lim - Singapore, SG
Tae Jong Lee - Orlando FL
Lap Chan - San Francisco CA

Assignee:

Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 2144

US Classification:

438687, 438624, 438625, 438626, 438627, 438629, 438631, 438633, 438637, 438638, 438666, 438669, 438672, 438675

Abstract:

A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

US Patent:

6380088, Apr 30, 2002

Filed:

Jan 19, 2001

Appl. No.:

09/764241

Inventors:

Lap Chan - San Francisco CA
Elgin Quek - Singapore, SG
Ravi Sundaresan - San Jose CA
Yang Pan - Singapore, SG
James Yong Meng Lee - Singapore, SG
Ying Keung Leung - Aberdeen, HK
Yelehanka Ramachandramurthy Pradeep - Singapore, SG
Jia Zhen Zheng - Singapore, SG

Assignee:

Chartered Semiconductor Manufacturing, Inc. - Milpitas CA

International Classification:

H01L 21302

US Classification:

438694, 438696, 438697, 438699, 438700, 438701

Abstract:

An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

US Patent:

6384437, May 7, 2002

Filed:

Sep 27, 2001

Appl. No.:

09/963411

Inventors:

Kheng Chok Tee - Selangor, MY
Randall Cher Liang Cha - Singapore, SG
Lap Chan - San Francisco CA

Assignee:

Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 27148

US Classification:

257239, 257296, 257304, 438705, 438253

Abstract:

Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si N hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance.

US Patent:

6387747, May 14, 2002

Filed:

May 31, 2001

Appl. No.:

09/867561

Inventors:

Randall Cha - Singapore, SG
Tae Jong Lee - Orlando FL
Alex See - Singapore, SG
Lap Chan - San Francisco CA
Chua Chee Tee - Singapore, SG

Assignee:

Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 218244

US Classification:

438238, 438381, 438687

Abstract:

A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.

US Patent:

6387784, May 14, 2002

Filed:

Mar 19, 2001

Appl. No.:

09/810121

Inventors:

Yung Fu Chong - Singapore, SG
Randall Cher Liang Cha - Singapore, SG
Lap Chan - San Francisco CA
Kin Leong Pey - Singapore, SG

Assignee:

Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 214763

US Classification:

438585, 438593

Abstract:

A method is provided to reduce poly depletion in MOS transistors. Conventionally, after a polysilicon electrode has been doped, an anneal step is usually performed to activate the dopants. However, the anneal step may be insufficient to drive the implanted impurities down the entire depth of the polysilicon electrode. Consequently, a portion of the polysilicon gate nearest to the gate oxide will be depleted of dopants. This poly depletion will have a detrimental effect on the control of the threshold voltage, and hence on the performance of the device. It is disclosed in the present invention a method of forming polysilicon gates where dopant depletion at the interface near the gate oxide layer is alleviated substantially by using laser annealing; however, by first pre-amorphizing the polycrystalline silicon prior to ion (implantation to a desired depth such that during laser annealing the dopants will diffuse uniformly to a melt depth. In this manner, poly depletion effect is greatly reduced and hence performance of the device improved. The disclosed method is applicable to both n doped polysilicon gates (NMOS) and p doped polysilicon gates (PMOS).

US Patent:

6403484, Jun 11, 2002

Filed:

Mar 12, 2001

Appl. No.:

09/803187

Inventors:

Victor Seng Keong Lim - Singapore, SG
Lap Chan - San Francisco CA
James Lee - Singapore, SG
Chen Feng - Singapore, SG
Wang Ling Goh - Singapore, SG

Assignee:

Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 2100

US Classification:

438692, 216 38, 216 79, 216 88, 216 99, 438723, 438745, 438756, 438757

Abstract:

A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed.

US Patent:

6403485, Jun 11, 2002

Filed:

May 2, 2001

Appl. No.:

09/846177

Inventors:

Elgin Quek - Singapore, SG
Ravi Sundaresan - San Jose CA
Yang Pan - Singapore, SG
James Lee Yong Meng - Singapore, SG
Ying Keung - Hong Kong, HK
Yelehanka Ramachandramurthy Pradeep - Singapore, SG
Jia Zhen Zheng - Singapore, SG
Lap Chan - San Francisco CA

Assignee:

Chartered Semiconductor Manufacturing Ltd - Singapore

International Classification:

H01L 21302

US Classification:

438692, 438694, 438696, 438700, 438704

Abstract:

A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas.