Joseph R Gomez

US Patent:

7017081, Mar 21, 2006

Filed:

Sep 27, 2002

Appl. No.:

10/259111

Inventors:

Joseph Jonas Gomez - Aurora IL, US

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 11/00

US Classification:

714 30

Abstract:

JTAG operations are carried out remotely over a network interface. The host processor includes a JTAG interpreter and a host side JTAG driver. A target device includes a target side JTAG driver. The interpreter processes and translates JTAG design files. The host side JTAG driver generates messages for the target side JTAG driver based on the translation. The host JTAG driver delivers the messages to a host network interface. The host network interface is connected via a network link to a target network interface. The target network interface is connected to the target side JTAG driver. The target side JTAG driver communicates with a target boundary scan chain. The target side JTAG driver and host side JTAG driver communicate over the network link. Network overhead is reduced by buffering messages until a message requiring a return of test data is ready for transmission.

US Patent:

7127708, Oct 24, 2006

Filed:

Mar 28, 2002

Appl. No.:

10/109083

Inventors:

Joseph J. Gomez - Naperville IL, US

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G06F 9/44
G06F 15/00

US Classification:

717139, 717127, 717131, 712 37

Abstract:

A method for programming of a plurality of programmable devices arranged in a JTAG boundary scan chain takes advantage of knowledge of a target system. The method speeds device programming and reduces system memory requirements. Raw data is extracted from high-level files. The raw data is stored in the target system. JTAG boundary scan chain information is coded into device programming software. Alternatively, the JTAG chain information is stored as data in the target system. The device programming software treats JTAG I/O registers of the programmable devices as concatenated shift registers. Data packets are assembled that include, for example, a byte of programming information, for each of the devices. The packets are shifted through into the JTAG chain. Bytes of the packet are aligned with, and loaded into, respective devices.

US Patent:

7661048, Feb 9, 2010

Filed:

Jun 29, 2007

Appl. No.:

11/770862

Inventors:

Joseph Jonas Gomez - Naperville IL, US
Kendall T. Krueger - Naperville IL, US
Greg A. Martin - Lisle IL, US
Robert Paul Tarr - Saint Charles IL, US

Assignee:

Alcatel-Lucent USA Inc. - Murray Hill NJ

International Classification:

G01R 31/28

US Classification:

714727

Abstract:

Embedded boundary scan testing apparatus and methodologies are disclosed for testing processor-based circuit boards without processor intervention. A boundary scan controller is embedded in a circuit board along with a boundary scan chain having JTAG devices connected with an electrical circuit of the board. Upon power up, the boundary scan controller holds an on-board processor system in reset, loads boundary scan test vectors and commands from an on-board non-volatile memory, and runs boundary scan testing while holding the processor system in the reset state. The boundary scan controller preferably includes a test access port controller that implements only a subset of the JTAG standard 16 machine states to optimize performance and minimize controller hardware. The test results may be stored in an externally accessible on-board memory for subsequent retrieval in order to facilitate board troubleshooting and/or repair, where the provision of on-board boundary scan testing allows testing of boards while installed in the field, and the embedded scan controller allows field testing of on-board processor systems and related circuitry to enhance the test coverage over processor-driven boundary scan testing.