Joseph D Rutkowski

US Patent:

7859314, Dec 28, 2010

Filed:

Mar 31, 2007

Appl. No.:

12/294982

Inventors:

Joseph Rutkowski - Chandler AZ, US
Alma Anderson - Chandler AZ, US

Assignee:

NXP B.V. - Eindhoven

International Classification:

H03B 1/00

US Classification:

327108, 326 83

Abstract:

Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor () from a gate of a transistor () using an isolation switch (). The transistor () is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor () using a charge distribution capacitor () that is selectively coupled to the feedback capacitor () using a switch (). The switch () is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor () reaching a reference voltage.

US Patent:

7940102, May 10, 2011

Filed:

Apr 30, 2010

Appl. No.:

12/770793

Inventors:

Alma Anderson - Chandler AZ, US
Joseph Rutkowski - Chandler AZ, US
Dave Oehler - Gilbert AZ, US

Assignee:

NXP B.V. - Eindhoven

International Classification:

H03K 5/12

US Classification:

327170

Abstract:

Consistent with an example embodiment, an edge-rate control circuit arrangement () for an I2C bus application comprises a first circuit stage (, M, M), responsive to a state transition of a received signal. A second circuit stage (, M, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (, R, R, M, M) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

US Patent:

20090066381, Mar 12, 2009

Filed:

Feb 24, 2006

Appl. No.:

11/816710

Inventors:

Alma Anderson - Chandler AZ, US
Joseph Rutkowski - Chandler AZ, US
Dave Oehler - Gilbert AZ, US

Assignee:

NXP B.V. - Eindhoven

International Classification:

H03K 5/01

US Classification:

327170

Abstract:

In an IC bus, an edge rate control for an output slows the falling edge of a signal. In an example embodiment, there is an edge rate control circuit for use in an IC bus. The circuit comprises a resistor divider having a first terminal, a divider terminal, and a second terminal. There is a first NMOS transistor having a source, drain, and gate terminal and a first PMOS transistor having a source, drain, and gate terminal; the source terminals of the first NMOS and first PMOS transistors are coupled to one another; the drain terminal of the first PMOS transistor is coupled to the divider terminal of the resistor divider; the gate of the first PMOS transistor is coupled to the second terminal of the resistor divider; and the drain of the first NMOS transistor is coupled to ground.

US Patent:

20220224269, Jul 14, 2022

Filed:

Jan 13, 2021

Appl. No.:

17/148100

Inventors:

- San Diego CA, US
Joseph Dale RUTKOWSKI - Chandler AZ, US
Joshua ZAZZERA - Chandler AZ, US
Nathaniel SALAZAR - San Diego CA, US

International Classification:

H02P 25/034
G08B 6/00

Abstract:

In some implementations, a measurement circuit may drive, using a first transistor, a first node of a haptic load. The measurement circuit may trigger a first comparator when a voltage driving the haptic load satisfies a first condition. The first comparator may have a first node connected, in parallel, to a drain of a second transistor and may have a second node connected to the first node of the haptic load. Additionally, the second transistor may have a gate connected to a gate of the first transistor and may have the drain connected to a first reference current.

US Patent:

20230089910, Mar 23, 2023

Filed:

Sep 22, 2021

Appl. No.:

17/448475

Inventors:

- San Diego CA, US
Chengwu Tao - Palo Alto CA, US
Joseph Dale Rutkowski - Chandler AZ, US

International Classification:

H02M 3/158
H02M 1/00

Abstract:

An apparatus is disclosed for a switch-mode power supply with a network of flying capacitors and switches. In an example aspect, the apparatus includes a switch-mode power supply with an inductor, a switching circuit, and a network of flying capacitors and switches. The switching circuit is coupled to the inductor. The network of flying capacitors and switches is coupled to the switching circuit and includes at least two flying capacitors and multiple switches. The multiple switches are configured to selectively connect the at least two flying capacitors in parallel between a first terminal of the network of flying capacitors and switches and a second terminal of the network of flying capacitors and switches or connect the at least two flying capacitors in series between the first terminal and the second terminal.

US Patent:

20230066436, Mar 2, 2023

Filed:

Aug 31, 2021

Appl. No.:

17/462243

Inventors:

- San Diego CA, US
Joseph Dale Rutkowski - Chandler AZ, US

International Classification:

H02M 3/158
H02J 7/00
H02M 1/00
G09G 3/20

Abstract:

An apparatus is disclosed for voltage regulation. In example implementations, an apparatus includes a battery subsystem having a first terminal, a second terminal, a third terminal, and at least one battery. The apparatus also includes a voltage regulator that is coupled to the first terminal, the second terminal, and the third terminal. The voltage regulator includes multiple switches, an energy storage unit, and control circuitry. The multiple switches include a first switch coupled to the first terminal, a second switch coupled to the second terminal, and a third switch coupled to the third terminal. The energy storage unit is coupled to the multiple switches. The control circuitry is coupled to the multiple switches and is configured to selectively couple the energy storage unit to the first terminal via the first switch, the second terminal via the second switch, or the third terminal via the third switch.

US Patent:

20200287465, Sep 10, 2020

Filed:

Mar 7, 2019

Appl. No.:

16/295449

Inventors:

- San Diego CA, US
Joseph Dale RUTKOWSKI - Chandler AZ, US

International Classification:

H02M 3/335
H02M 1/14
H03K 4/62

Abstract:

Certain aspects of the present disclosure generally relate to a switch mode power supply (SMPS). The SMPS generally includes at least one switch, an inductive element coupled to the at least one switch, and control circuitry, the control circuitry being configured to control the at least one switch, during each switching cycle of a plurality switching cycles of the SMPS, to transfer charge from an input voltage (Vin) node of the SMPS to the inductive element during an on-time of the switching cycle and transfer the charge to an output voltage (Vout) node of the SMPS during an off-time of the switching cycle. The on-time may be set based on a duty ratio of the SMPS, the duty ratio representing a ratio between a voltage at the Vin node and a voltage at the Vout node, the on-time being fixed depending on the duty ratio of the SMPS.

US Patent:

20200073425, Mar 5, 2020

Filed:

Aug 28, 2019

Appl. No.:

16/554082

Inventors:

- San Diego CA, US
Sivaprasad EMBANATH - Singapore, SG
Joseph Dale RUTKOWSKI - Chandler AZ, US

International Classification:

G05F 1/575
G05F 1/565

Abstract:

Certain aspects of the present disclosure generally relate to methods and apparatus for switching between modes of a multi-mode power supply circuit. One example power supply circuit generally includes a switched-mode power supply (SMPS) circuit, a voltage regulator circuit having an input coupled to an output of the SMPS circuit, the voltage regulator circuit being configured to be selectively enabled, a first voltage divider selectively coupled to the output of the SMPS circuit and selectively coupled to an output of the voltage regulator circuit, and a second voltage divider coupled to the output of the voltage regulator circuit.