Judith Suzanne Richardson

US Patent:

20090271750, Oct 29, 2009

Filed:

Nov 30, 2006

Appl. No.:

12/095164

Inventors:

Judith Richardson - Saratoga CA, US
Niranjan A. Puttaswamy - Santa Clara CA, US

Assignee:

NXP B.V. - Eindhoven

International Classification:

G06F 17/50

US Classification:

716 6

Abstract:

A method for propagating timing constraints from lower level design blocks to higher level design blocks includes o the steps of designing a circuit containing a plurality of design blocks. Each of the plurality of design blocks has a set of timing constraints associated therewith. A composite set of timing constraints is created for the circuit from each of the set of timing constraints associated with each of the plurality of design blocks, according to an established propagation rule set.