Stephen Mark Edwards

US Patent:

20230101154, Mar 30, 2023

Filed:

Dec 2, 2022

Appl. No.:

18/074167

Inventors:

- Shenzhen, CN
Michael Vaden - Austin TX, US
Jingliang Wang - Austin TX, US
Noah Sherrill - Austin TX, US
Stephen Edwards - Austin TX, US

International Classification:

G06F 11/36

Abstract:

A method for generating instruction sequences for testing a processor design model. The method includes receiving, by an instruction sequence generator (ISG), an initial test template. The initial test template includes an initial set of instruction constraints and a save resumable state command. The ISG generates a first set of executable test instructions based on the initial test template. The ISG initiates the save resumable state command. The ISG creates and saves a snapshot that includes information on a resume state of the ISG and the first set of executable test instructions at the time the save resumable state command is initiated.

Address:

800 Ethel St, Austin, TX 78704

Phone:

5129128046

VIN:

JTDKB20U477664238

Make:

TOYOTA

Model:

PRIUS

Year:

2007