Michael P Ching

US Patent:

6342800, Jan 29, 2002

Filed:

Oct 26, 2000

Appl. No.:

09/698997

Inventors:

Donald C. Stark - Palo Alot CA
Jun Kim - Redwood City CA
Kurt T. Knorpp - San Carlos CA
Michael Tak-Kei Ching - Sunnyvale CA
Natsuki Kushiyama - Yokohama, JP

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H03K 512

US Classification:

327170, 327175

Abstract:

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

US Patent:

6473439, Oct 29, 2002

Filed:

Oct 9, 1998

Appl. No.:

09/169372

Inventors:

Jared LeVan Zerbe - Palo Alto CA
Michael Tak-kei Ching - Sunnyvale CA
Abhijit M. Abhyankar - Sunnyvale CA
Richard M. Barth - Palo Alto CA
Andy Peng-Pui Chan - San Jose CA
Paul G. Davis - San Jose CA
William F. Stonecypher - San Jose CA

Assignee:

Rambus Incorporated - Los Altos CA

International Classification:

H04J 306

US Classification:

370503, 713400, 713600

Abstract:

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

US Patent:

6556052, Apr 29, 2003

Filed:

Sep 12, 2001

Appl. No.:

09/954561

Inventors:

John B. Dillon - late of Palo Alto CA
Michael Tak-Kei Ching - Sunnyvale CA 94086
William F. Stonecypher - San Jose CA 95118
Andy Peng-Pui Chan - San Jose CA 95132
Matthew M. Griffin - Mountain View CA 94043

International Classification:

H03B 100

US Classification:

327108, 327530

Abstract:

A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.

US Patent:

6608507, Aug 19, 2003

Filed:

Aug 29, 2002

Appl. No.:

10/230931

Inventors:

John B. Dillon - late of Palo Alto CA
Michael Tak-Kei Ching - Sunnyvale CA
William F. Stonecypher - San Jose CA
Andy Peng-Pui Chan - San Jose CA
Matthew M. Griffin - Mountain View CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H03B 100

US Classification:

327108, 327535

Abstract:

A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode. The memory device is operable in a normal read operation upon exiting the calibration mode.

US Patent:

6661268, Dec 9, 2003

Filed:

Dec 11, 2001

Appl. No.:

10/014650

Inventors:

Donald C. Stark - Palo Alto CA
Jun Kim - Redwood City CA
Kurt T. Knorpp - San Carlos CA
Michael Tak-Kei Ching - Sunnyvale CA
Natsuki Kushiyama - Yokohama, JP

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H03K 512

US Classification:

327170, 327538

Abstract:

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

US Patent:

6922092, Jul 26, 2005

Filed:

Dec 8, 2003

Appl. No.:

10/731718

Inventors:

Donald C. Stark - Palo Alto CA, US
Jun Kim - Redwood City CA, US
Kurt T. Knorpp - San Carlos CA, US
Michael Tak-Kei Ching - Sunnyvale CA, US
Natsuki Kushiyama - Yokohama, JP

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H03K005/12

US Classification:

327170, 327538

Abstract:

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

US Patent:

6949958, Sep 27, 2005

Filed:

Oct 28, 2002

Appl. No.:

10/282531

Inventors:

Jared LeVan Zerbe - Palo Alto CA, US
Michael Tak-kei Ching - Sunnyvale CA, US
Abhijit M. Abhyankar - Sunnyvale CA, US
Richard M. Barth - Palo Alto CA, US
Andy Peng-Pui Chan - San Jose CA, US
Paul G. Davis - San Jose CA, US
William F. Stonecypher - San Jose CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G01R025/00

US Classification:

327 3, 327 7, 327 40, 327 42, 375375, 324 7678

Abstract:

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

US Patent:

6975159, Dec 13, 2005

Filed:

Nov 5, 2004

Appl. No.:

10/981808

Inventors:

Michael Tak-Kei Ching - Sunnyvale CA, US
Andy Peng-Pui Chan - San Jose CA, US
Matthew M. Griffin - Mountain View CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G05F001/10

US Classification:

327535

Abstract:

A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.