Christopher Lee Colletti - Austin TX, US Bryan Glen Hickerson - Cedar Park TX, US Michael Joseph Schiffli - Round Rock TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/30
US Classification:
712227, 712220, 712E09016
Abstract:
A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.