Nghia T Tran

US Patent:

RE40011, Jan 22, 2008

Filed:

Oct 19, 2001

Appl. No.:

10/084757

Inventors:

Nghia Tran - Milpitas CA, US
Ying Xuan Li - Cupertino CA, US
Janusz Balicki - San Jose CA, US
John Costello - Los Altos CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 46, 326 40

Abstract:

A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e. g. , 0. 4 volts to 2. 4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e. g. , 0. 8 volts to 1. 2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.

US Patent:

55508421, Aug 27, 1996

Filed:

Oct 28, 1994

Appl. No.:

8/330761

Inventors:

Nghia Tran - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 2900

US Classification:

371 214

Abstract:

The present invention provides a verification circuit for EEPROM cells by connecting PMOS verify transistors in parallel across the EEPROM cells to be tested. This configuration occupies less space on a PLD chip than prior verification circuits and allows all EEPROM bits associated with one logic cell in the PLD to be coupled to one verify path, minimizing logic complexity.

US Patent:

59702559, Oct 19, 1999

Filed:

Oct 16, 1995

Appl. No.:

8/543649

Inventors:

Nghia Tran - San Jose CA
Ying Xuan Li - Santa Clara CA
Janusz Balicki - San Jose CA
John Costello - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1310

US Classification:

395893

Abstract:

A programmable input/output device for use with a programmable logic device (PLD) is presented comprising an input buffer, an output buffer and programmable elements. The programmable elements may be programmed to select a logic standard for the input/output device to operate at. For instance, a given set of Select Bits applied to the programmable elements may select TTL logic, in which case the input and output buffers would operate according to the voltage levels appropriate for TTL logic (e. g. , 0. 4 volts to 2. 4 volts). For a different set of Select Bits, the GTL logic standard would be applied (e. g. , 0. 8 volts to 1. 2 volts). The invention enables a single PLD to be used in conjunction with various types of external circuitry.